From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org, "Alistair Francis" <alistair23@gmail.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: Re: [PULL 00/37] riscv-to-apply queue
Date: Thu, 23 Oct 2025 13:15:37 -0500 [thread overview]
Message-ID: <325c46b7-54fd-4793-95f1-2dc6cc44869c@linaro.org> (raw)
In-Reply-To: <20251023041435.1775208-1-alistair.francis@wdc.com>
On 10/22/25 23:13, alistair23@gmail.com wrote:
> From: Alistair Francis<alistair.francis@wdc.com>
>
> The following changes since commit c0e80879c876cbe4cbde43a92403329bcedf2ba0:
>
> Merge tag 'pull-vfio-20251022' ofhttps://github.com/legoater/qemu into staging (2025-10-22 08:01:21 -0500)
>
> are available in the Git repository at:
>
> https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20251023
>
> for you to fetch changes up to 741566c3e07fd34ed28d4464d1d7fda67db12925:
>
> target/riscv: Make PMP CSRs conform to WARL constraints (2025-10-23 14:11:45 +1000)
>
> ----------------------------------------------------------------
> Second RISC-V PR for 10.2
>
> * Correct mmu-type property of sifive_u harts in device tree
> * Centralize MO_TE uses in a pair of helpers
> * Fix Ethernet interface support for microchip-icicle-kit
> * Fix mask for smsiaddrcfgh
> * Add support for MIPS P8700 CPU
> * Fix env->priv setting in reset_regs_csr()
> * Coverity-related fixes
> * Fix riscv_cpu_sirq_pending() mask
> * Fix a uninitialized variable warning
> * Make PMP granularity configurable
Something in here is causing failures on s390x:
https://gitlab.com/qemu-project/qemu/-/jobs/11827080939#L5859
It seems obvious to suspect the endianness changes from the big-endian host, but I also
don't immediately see anything wrong.
r~
next prev parent reply other threads:[~2025-10-23 18:16 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-23 4:13 [PULL 00/37] riscv-to-apply queue alistair23
2025-10-23 4:13 ` [PULL 01/37] hw/riscv: Correct mmu-type property of sifive_u harts in device tree alistair23
2025-10-23 4:14 ` [PULL 02/37] target/riscv: Explode MO_TExx -> MO_TE | MO_xx alistair23
2025-10-23 4:14 ` [PULL 03/37] target/riscv: Conceal MO_TE within gen_amo() alistair23
2025-10-23 4:14 ` [PULL 04/37] target/riscv: Conceal MO_TE within gen_inc() alistair23
2025-10-23 4:14 ` [PULL 05/37] target/riscv: Conceal MO_TE within gen_load() / gen_store() alistair23
2025-10-23 4:14 ` [PULL 06/37] target/riscv: Conceal MO_TE within gen_load_idx() / gen_store_idx() alistair23
2025-10-23 4:14 ` [PULL 07/37] target/riscv: Conceal MO_TE within gen_fload_idx() / gen_fstore_idx() alistair23
2025-10-23 4:14 ` [PULL 08/37] target/riscv: Conceal MO_TE within gen_storepair_tl() alistair23
2025-10-23 4:14 ` [PULL 09/37] target/riscv: Conceal MO_TE within gen_cmpxchg*() alistair23
2025-10-23 4:14 ` [PULL 10/37] target/riscv: Conceal MO_TE|MO_ALIGN within gen_lr() / gen_sc() alistair23
2025-10-23 4:14 ` [PULL 11/37] target/riscv: Factor MemOp variable out when MO_TE is set alistair23
2025-10-23 4:14 ` [PULL 12/37] target/riscv: Introduce mo_endian() helper alistair23
2025-10-23 4:14 ` [PULL 13/37] target/riscv: Introduce mo_endian_env() helper alistair23
2025-10-23 4:14 ` [PULL 14/37] hw/net/cadence_gem: Support two Ethernet interfaces connected to single MDIO bus alistair23
2025-10-23 4:14 ` [PULL 15/37] hw/riscv: microchip_pfsoc: Connect Ethernet PHY channels alistair23
2025-10-23 4:14 ` [PULL 16/37] hw/net/cadence_gem: Add pcs-enabled property alistair23
2025-10-23 4:14 ` [PULL 17/37] microchip icicle: Enable PCS on Cadence Ethernet alistair23
2025-10-23 4:14 ` [PULL 18/37] aplic: fix mask for smsiaddrcfgh alistair23
2025-10-23 4:14 ` [PULL 19/37] hw/intc: Allow gaps in hartids for aclint and aplic alistair23
2025-10-23 4:14 ` [PULL 20/37] target/riscv: Add cpu_set_exception_base alistair23
2025-10-23 4:14 ` [PULL 21/37] target/riscv: Add MIPS P8700 CPU alistair23
2025-10-23 18:15 ` Richard Henderson [this message]
2025-10-23 23:44 ` [PULL 00/37] riscv-to-apply queue Alistair Francis
-- strict thread matches above, loose matches on Subject: below --
2023-01-20 7:38 Alistair Francis
2023-01-21 13:01 ` Peter Maydell
2022-01-08 5:50 Alistair Francis
2022-01-08 17:37 ` Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=325c46b7-54fd-4793-95f1-2dc6cc44869c@linaro.org \
--to=richard.henderson@linaro.org \
--cc=alistair23@gmail.com \
--cc=philmd@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).