From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:59364) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UU98z-00050D-Jf for qemu-devel@nongnu.org; Mon, 22 Apr 2013 01:18:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UU98w-0004e2-Ms for qemu-devel@nongnu.org; Mon, 22 Apr 2013 01:18:25 -0400 Received: from mail-pd0-f180.google.com ([209.85.192.180]:42190) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UU98w-0004dt-Hk for qemu-devel@nongnu.org; Mon, 22 Apr 2013 01:18:22 -0400 Received: by mail-pd0-f180.google.com with SMTP id q11so3317421pdj.11 for ; Sun, 21 Apr 2013 22:18:21 -0700 (PDT) Sender: Peter Crosthwaite From: peter.crosthwaite@xilinx.com Date: Mon, 22 Apr 2013 15:16:30 +1000 Message-Id: <325c8316b51c4c0d7835bea7adf87df40337abf3.1366606958.git.peter.crosthwaite@xilinx.com> In-Reply-To: References: Subject: [Qemu-devel] [PATCH for-1.5 v3 08/15] xilinx_spips: Implement automatic CS List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, edgar.iglesias@gmail.com From: Peter Crosthwaite Implement the automatic CS control feature. If the MANUAL_CS bit is cleared then the chip select stay de-asserted as long as the tx FIFO is empty. Signed-off-by: Peter Crosthwaite Reviewed-by: Peter Maydell --- changed from v1: Refresh CS on entry and exit from flush routine as needed. hw/ssi/xilinx_spips.c | 18 ++++++++++++++---- 1 files changed, 14 insertions(+), 4 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 5580e67..3f31a32 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -190,6 +190,12 @@ static inline int num_effective_busses(XilinxSPIPS *s) s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1; } +static inline bool xilinx_spips_cs_is_set(XilinxSPIPS *s, int i, int field) +{ + return ~field & (1 << i) && (s->regs[R_CONFIG] & MANUAL_CS + || !fifo8_is_empty(&s->tx_fifo)); +} + static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) { int i, j; @@ -202,14 +208,15 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) int cs_to_set = (j * s->num_cs + i + upage) % (s->num_cs * s->num_busses); - if (~field & (1 << i) && !found) { + if (xilinx_spips_cs_is_set(s, i, field) && !found) { DB_PRINT("selecting slave %d\n", i); qemu_set_irq(s->cs_lines[cs_to_set], 0); } else { + DB_PRINT_L(0, "deselecting slave %d\n", i); qemu_set_irq(s->cs_lines[cs_to_set], 1); } } - if (~field & (1 << i)) { + if (xilinx_spips_cs_is_set(s, i, field)) { found = true; } } @@ -451,12 +458,13 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, } s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); no_reg_update: + xilinx_spips_update_cs_lines(s); if ((man_start_com && s->regs[R_CONFIG] & MAN_START_EN) || (fifo8_is_empty(&s->tx_fifo) && s->regs[R_CONFIG] & MAN_START_EN)) { xilinx_spips_flush_txfifo(s); } - xilinx_spips_update_ixr(s); xilinx_spips_update_cs_lines(s); + xilinx_spips_update_ixr(s); } static const MemoryRegionOps spips_ops = { @@ -510,7 +518,7 @@ lqspi_read(void *opaque, hwaddr addr, unsigned int size) fifo8_reset(&s->rx_fifo); s->regs[R_CONFIG] &= ~CS; - s->regs[R_CONFIG] |= (~(1 << slave) << CS_SHIFT) & CS; + s->regs[R_CONFIG] |= ((~(1 << slave) << CS_SHIFT) & CS) | MANUAL_CS; xilinx_spips_update_cs_lines(s); /* instruction */ @@ -534,6 +542,7 @@ lqspi_read(void *opaque, hwaddr addr, unsigned int size) DB_PRINT("pushing dummy byte\n"); fifo8_push(&s->tx_fifo, 0); } + xilinx_spips_update_cs_lines(s); xilinx_spips_flush_txfifo(s); fifo8_reset(&s->rx_fifo); @@ -545,6 +554,7 @@ lqspi_read(void *opaque, hwaddr addr, unsigned int size) rx_data_bytes(s, &q->lqspi_buf[cache_entry], 4); cache_entry++; } + xilinx_spips_update_cs_lines(s); s->regs[R_CONFIG] |= CS; xilinx_spips_update_cs_lines(s); -- 1.7.0.4