From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com
Subject: Re: [PATCH v5 10/22] target/riscv: Create current pm fields in env
Date: Fri, 26 Nov 2021 12:31:04 +0100 [thread overview]
Message-ID: <32c4e078-bb8c-07fe-d69e-cdbd725d4726@linaro.org> (raw)
In-Reply-To: <20211125073951.57678-11-zhiwei_liu@c-sky.com>
On 11/25/21 8:39 AM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
> Reviewed-by: Alistair Francis<alistair.francis@wdc.com>
> ---
> target/riscv/cpu.c | 1 +
> target/riscv/cpu.h | 4 ++++
> target/riscv/cpu_helper.c | 43 +++++++++++++++++++++++++++++++++++++++
> target/riscv/csr.c | 19 +++++++++++++++++
> target/riscv/machine.c | 10 +++++++++
> 5 files changed, 77 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2021-11-26 11:32 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-25 7:39 [PATCH v5 00/22] Support UXL filed in xstatus LIU Zhiwei
2021-11-25 7:39 ` [PATCH v5 01/22] target/riscv: Adjust pmpcfg access with mxl LIU Zhiwei
2021-11-26 11:19 ` Richard Henderson
2021-11-25 7:39 ` [PATCH v5 02/22] target/riscv: Don't save pc when exception return LIU Zhiwei
2021-11-25 7:39 ` [PATCH v5 03/22] target/riscv: Sign extend pc for different XLEN LIU Zhiwei
2021-11-25 7:39 ` [PATCH v5 04/22] target/riscv: Create xl field in env LIU Zhiwei
2021-11-26 11:25 ` Richard Henderson
2021-11-25 7:39 ` [PATCH v5 05/22] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2021-11-25 7:39 ` [PATCH v5 06/22] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2021-11-25 7:39 ` [PATCH v5 07/22] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2021-11-25 7:39 ` [PATCH v5 08/22] target/riscv: Relax debug check for pm write LIU Zhiwei
2021-11-25 7:39 ` [PATCH v5 09/22] target/riscv: Adjust csr write mask with XLEN LIU Zhiwei
2021-11-25 7:39 ` [PATCH v5 10/22] target/riscv: Create current pm fields in env LIU Zhiwei
2021-11-26 11:31 ` Richard Henderson [this message]
2021-11-25 7:39 ` [PATCH v5 11/22] target/riscv: Alloc tcg global for cur_pm[mask|base] LIU Zhiwei
2021-11-25 7:39 ` [PATCH v5 12/22] target/riscv: Calculate address according to XLEN LIU Zhiwei
2021-11-25 7:39 ` [PATCH v5 13/22] target/riscv: Split pm_enabled into mask and base LIU Zhiwei
2021-11-25 7:39 ` [PATCH v5 14/22] target/riscv: Split out the vill from vtype LIU Zhiwei
2021-11-25 7:39 ` [PATCH v5 15/22] target/riscv: Fix RESERVED field length in VTYPE LIU Zhiwei
2021-11-25 7:39 ` [PATCH v5 16/22] target/riscv: Adjust vsetvl according to XLEN LIU Zhiwei
2021-11-25 7:39 ` [PATCH v5 17/22] target/riscv: Remove VILL field in VTYPE LIU Zhiwei
2021-11-25 7:39 ` [PATCH v5 18/22] target/riscv: Ajdust vector atomic check with XLEN LIU Zhiwei
2021-11-25 7:39 ` [PATCH v5 19/22] target/riscv: Fix check range for first fault only LIU Zhiwei
2021-11-25 7:39 ` [PATCH v5 20/22] target/riscv: Adjust vector address with mask LIU Zhiwei
2021-11-26 11:33 ` Richard Henderson
2021-11-25 7:39 ` [PATCH v5 21/22] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei
2021-11-25 7:39 ` [PATCH v5 22/22] target/riscv: Enable uxl field write LIU Zhiwei
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