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From: Richard Henderson <richard.henderson@linaro.org>
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Date: Sat, 25 Aug 2018 09:50:40 -0700
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Subject: Re: [Qemu-devel] [PATCH 1/7] target/mips: Add MXU register support
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To: Craig Janeczek <jancraig@amazon.com>, qemu-devel@nongnu.org
Cc: aurelien@aurel32.net, amarkovic@wavecomp.com

On 08/24/2018 12:44 PM, Craig Janeczek via Qemu-devel wrote:
> +/* MXU General purpose registers moves. */
> +static inline void gen_load_mxu_gpr (TCGv t, int reg)
> +{
> +    if (reg == 0)
> +        tcg_gen_movi_tl(t, 0);
> +    else
> +        tcg_gen_mov_tl(t, mxu_gpr[reg-1]);
> +}
> +
> +static inline void gen_store_mxu_gpr (TCGv t, int reg)
> +{
> +    if (reg != 0)
> +        tcg_gen_mov_tl(mxu_gpr[reg-1], t);
> +}
> +
>  /* Moves to/from shadow registers. */
>  static inline void gen_load_srsgpr (int from, int to)
>  {
> @@ -20742,6 +20767,11 @@ void mips_tcg_init(void)
>      fpu_fcr31 = tcg_global_mem_new_i32(cpu_env,
>                                         offsetof(CPUMIPSState, active_fpu.fcr31),
>                                         "fcr31");
> +
> +    for (i = 0; i < 16; i++)
> +        mxu_gpr[i] = tcg_global_mem_new(cpu_env,
> +                                        offsetof(CPUMIPSState, active_tc.mxu_gpr[i]),
> +                                        mxuregnames[i]);
>  }

You need to fix the ./scripts/checkpatch.pl errors.
But otherwise the logic is ok.


r~