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From: Laurent DESNOGUES <laurent.desnogues@wanadoo.fr>
Subject: Re: [Qemu-devel] ARM CPU Speed simulated by Qemu?
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Date: Tue, 12 Sep 2006 17:08:33 +0200 (CEST)
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To: Markus Schiltknecht <markus@bluegap.ch>, qemu-devel@nongnu.org

> > The most complex thing to accurately simulate a modern
> > CPU (including ARMs) is the data cache and by far. 
> 
> Hm... you have to elaborate on that one. Aren't those caches like other 
> caches, too? With well known algorithms like LRU?

Data caches typically do many things in one cycle;  for
instance, if you make a load, it could start looking in
a small area between the cache and the core (called
write or store buffer) and at the same time look into
the real cache to find the data;  then depending on the
outcome, an external request could be started, this
cycle or later depending on previous requests still
pending.  And this is a simple example ;)

On top of that try to find a specification for data
side behaviour, these beasts are not documented for
two reasons:
- they are heavily optimized and so not easily
  described
- they often define the efficiency of a CPU and
  so are considered as secret.

> Simulating branch prediction seems more complex to me (probably because 
> I'm thinking x86, not ARM).

Branch prediction has become very complex on ARM
but not as much as data side.


Laurent