From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1457CC4361B for ; Fri, 18 Dec 2020 10:45:23 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 92DF023A5B for ; Fri, 18 Dec 2020 10:45:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 92DF023A5B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:54634 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqDGD-0006a2-FQ for qemu-devel@archiver.kernel.org; Fri, 18 Dec 2020 05:45:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46602) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kqD8W-0005Ms-65; Fri, 18 Dec 2020 05:37:24 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:55232 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqD8T-00036A-Vo; Fri, 18 Dec 2020 05:37:23 -0500 Received: from basile.remlab.net (dzyqn8ypzhx7l91mxjsvy-3.rev.dnainternet.fi [IPv6:2001:14ba:a01a:be01:9434:f69e:d553:3be2]) (Authenticated sender: remi) by ns207790.ip-94-23-215.eu (Postfix) with ESMTPSA id 32FE25FA93; Fri, 18 Dec 2020 11:37:18 +0100 (CET) From: =?ISO-8859-1?Q?R=E9mi?= Denis-Courmont To: qemu-arm@nongnu.org Subject: [PATCHv4 00/18] ARMv8.4-A Secure EL2 Date: Fri, 18 Dec 2020 12:37:17 +0200 Message-ID: <3337797.iIbC2pHGDl@basile.remlab.net> Organization: Huawei Technologies, Finland MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi, The following changes since commit af3f37319cb1e1ca0c42842ecdbd1bcfc64a4b6f: Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' i= nto staging (2020-12-15 21:24:31 +0000) follow. Changes since version 3: =2D Drop unnecessary changes of arm_mmu_idx_is_stage1_of_2() prototype. =2D Fix RegimeEL() for S-EL0 on 32-bit. =2D Translate NS bit after stage 2, not before it - Should fix bizarre configurations of V(S)TCR.(N)S{A,W} bits. =2D Don't hard-code the list of stage 1 of 2 regimes. =2D--------------------------------------------------------------- R=C3=A9mi Denis-Courmont (18): target/arm: remove redundant tests target/arm: add arm_is_el2_enabled() helper target/arm: use arm_is_el2_enabled() where applicable target/arm: use arm_hcr_el2_eff() where applicable target/arm: factor MDCR_EL2 common handling target/arm: declare new AA64PFR0 bit-fields target/arm: add 64-bit S-EL2 to EL exception table target/arm: add MMU stage 1 for Secure EL2 target/arm: add ARMv8.4-SEL2 system registers target/arm: handle VMID change in secure state target/arm: do S1_ptw_translate() before address space lookup target/arm: translate NS bit in page-walks target/arm: generalize 2-stage page-walk condition target/arm: secure stage 2 translation regime target/arm: set HPFAR_EL2.NS on secure stage 2 faults target/arm: add ARMv8.4-SEL2 extension target/arm: enable Secure EL2 in max CPU target/arm: refactor vae1_tlbmask() target/arm/cpu-param.h | 2 +- target/arm/cpu.c | 10 +- target/arm/cpu.h | 93 ++++++++-- target/arm/cpu64.c | 1 + target/arm/helper-a64.c | 8 +- target/arm/helper.c | 419 ++++++++++++++++++++++++++++++-----------= =2D--- target/arm/internals.h | 36 ++++ target/arm/op_helper.c | 4 +- target/arm/tlb_helper.c | 3 + target/arm/translate-a64.c | 4 + target/arm/translate.c | 6 +- target/arm/translate.h | 1 + 12 files changed, 410 insertions(+), 177 deletions(-) =2D-=20 =E9=9B=B7=E7=B1=B3=E2=80=A7=E5=BE=B7=E5=B0=BC-=E5=BA=93=E5=B0=94=E8=92=99 http://www.remlab.net/