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[97.126.117.207]) by smtp.gmail.com with ESMTPSA id a21sm60770923pfi.27.2019.07.26.07.52.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 26 Jul 2019 07:52:11 -0700 (PDT) To: tony.nguyen@bt.com, qemu-devel@nongnu.org References: <3106a3c959c4498fad13a5799c89ba7b@tpw09926dag18e.domain1.systemhost.net> <1564123712210.75919@bt.com> From: Richard Henderson Openpgp: preference=signencrypt Message-ID: <3342e044-607c-0aaa-fe63-27500db68e71@linaro.org> Date: Fri, 26 Jul 2019 07:52:08 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <1564123712210.75919@bt.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: Re: [Qemu-devel] [PATCH v5 13/15] cputlb: Byte swap memory transaction attribute X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, walling@linux.ibm.com, sagark@eecs.berkeley.edu, mst@redhat.com, palmer@sifive.com, mark.cave-ayland@ilande.co.uk, Alistair.Francis@wdc.com, edgar.iglesias@gmail.com, alex.williamson@redhat.com, arikalo@wavecomp.com, david@redhat.com, pasic@linux.ibm.com, borntraeger@de.ibm.com, rth@twiddle.net, atar4qemu@gmail.com, ehabkost@redhat.com, qemu-s390x@nongnu.org, qemu-arm@nongnu.org, stefanha@redhat.com, shorne@gmail.com, david@gibson.dropbear.id.au, qemu-riscv@nongnu.org, kbastian@mail.uni-paderborn.de, cohuck@redhat.com, laurent@vivier.eu, qemu-ppc@nongnu.org, amarkovic@wavecomp.com, pbonzini@redhat.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 7/25/19 11:48 PM, tony.nguyen@bt.com wrote: > Notice new attribute, byte swap, and force the transaction through the > memory slow path. > > Required by architectures that can invert endianness of memory > transaction, e.g. SPARC64 has the Invert Endian TTE bit. > > Signed-off-by: Tony Nguyen > --- > accel/tcg/cputlb.c | 11 +++++++++++ > include/exec/memattrs.h | 2 ++ > 2 files changed, 13 insertions(+) > > diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c > index e61b1eb..f292a87 100644 > --- a/accel/tcg/cputlb.c > +++ b/accel/tcg/cputlb.c > @@ -738,6 +738,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, > */ > address |= TLB_RECHECK; > } > + if (attrs.byte_swap) { > + address |= TLB_FORCE_SLOW; > + } > if (!memory_region_is_ram(section->mr) && > !memory_region_is_romd(section->mr)) { > /* IO memory case */ > @@ -891,6 +894,10 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, > bool locked = false; > MemTxResult r; > > + if (iotlbentry->attrs.byte_swap) { > + op ^= MO_BSWAP; > + } > + > section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); > mr = section->mr; > mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; > @@ -933,6 +940,10 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, > bool locked = false; > MemTxResult r; > > + if (iotlbentry->attrs.byte_swap) { > + op ^= MO_BSWAP; > + } > + > section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); > mr = section->mr; > mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; > diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h > index d4a3477..a0644eb 100644 > --- a/include/exec/memattrs.h > +++ b/include/exec/memattrs.h > @@ -37,6 +37,8 @@ typedef struct MemTxAttrs { > unsigned int user:1; > /* Requester ID (for MSI for example) */ > unsigned int requester_id:16; > + /* SPARC64: TTE invert endianness */ > + unsigned int byte_swap:1; Don't mention Sparc here, otherwise it seems like it only applies to Sparc, when it is really a generic feature only currently used by Sparc. Just say "Invert endianness for this page". With that, Reviewed-by: Richard Henderson r~