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Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.14.0 Subject: Re: [PATCH 04/20] target/riscv: move riscv_tcg_ops to tcg-cpu.c Content-Language: en-US To: Daniel Henrique Barboza , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com References: <20230825130853.511782-1-dbarboza@ventanamicro.com> <20230825130853.511782-5-dbarboza@ventanamicro.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230825130853.511782-5-dbarboza@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.169, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 25/8/23 15:08, Daniel Henrique Barboza wrote: > Move the remaining of riscv_tcg_ops now that we have a working realize() > implementation. > > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/cpu.c | 58 ------------------------------------- > target/riscv/cpu.h | 4 --- > target/riscv/tcg/tcg-cpu.c | 59 ++++++++++++++++++++++++++++++++++++++ > 3 files changed, 59 insertions(+), 62 deletions(-) > +const struct TCGCPUOps riscv_tcg_ops = { > + .initialize = riscv_translate_init, > + .synchronize_from_tb = riscv_cpu_synchronize_from_tb, > + .restore_state_to_opc = riscv_restore_state_to_opc, > + > +#ifndef CONFIG_USER_ONLY > + .tlb_fill = riscv_cpu_tlb_fill, > + .cpu_exec_interrupt = riscv_cpu_exec_interrupt, > + .do_interrupt = riscv_cpu_do_interrupt, > + .do_transaction_failed = riscv_cpu_do_transaction_failed, > + .do_unaligned_access = riscv_cpu_do_unaligned_access, > + .debug_excp_handler = riscv_cpu_debug_excp_handler, > + .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, > + .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, > +#endif /* !CONFIG_USER_ONLY */ > +}; We can remove the "riscv_tcg_ops is being imported from cpu.c for now." comment in tcg_cpu_init_ops(), otherwise: Reviewed-by: Philippe Mathieu-Daudé