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Sun, 27 Oct 2024 17:42:45 GMT Received: from smtprelay06.wdc07v.mail.ibm.com ([172.16.1.73]) by ppma22.wdc07v.mail.ibm.com (PPS) with ESMTPS id 42hb4xjucy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 27 Oct 2024 17:42:45 +0000 Received: from smtpav04.dal12v.mail.ibm.com (smtpav04.dal12v.mail.ibm.com [10.241.53.103]) by smtprelay06.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 49RHgjco18219564 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sun, 27 Oct 2024 17:42:45 GMT Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2797258052; Sun, 27 Oct 2024 17:42:45 +0000 (GMT) Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A9A7F58056; Sun, 27 Oct 2024 17:42:44 +0000 (GMT) Received: from [9.47.158.152] (unknown [9.47.158.152]) by smtpav04.dal12v.mail.ibm.com (Postfix) with ESMTP; Sun, 27 Oct 2024 17:42:44 +0000 (GMT) Message-ID: <33618d67-861c-41aa-99d3-c610b59dc9e6@linux.ibm.com> Date: Sun, 27 Oct 2024 13:42:44 -0400 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/3] tests/qtest/tpm: add unit test to tis-spi To: dan tan , qemu-devel@nongnu.org, stefanb@linux.vnet.ibm.com, pbonzini@redhat.com, farosas@suse.de, lvivier@redhat.com, clg@kaod.org Cc: qemu-ppc@nongnu.org References: <20241025201247.29574-1-dantan@linux.vnet.ibm.com> <20241025201247.29574-4-dantan@linux.vnet.ibm.com> Content-Language: en-US From: Stefan Berger In-Reply-To: <20241025201247.29574-4-dantan@linux.vnet.ibm.com> Content-Type: text/plain; charset=UTF-8; format=flowed X-TM-AS-GCONF: 00 X-Proofpoint-GUID: kgQr0_SBerOuC6LTvAeIFlcSW_a1F7xC X-Proofpoint-ORIG-GUID: kgQr0_SBerOuC6LTvAeIFlcSW_a1F7xC Content-Transfer-Encoding: 7bit X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-10-15_01,2024-10-11_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 priorityscore=1501 mlxscore=0 clxscore=1015 phishscore=0 mlxlogscore=999 impostorscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410270155 Received-SPF: pass client-ip=148.163.156.1; envelope-from=stefanb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/25/24 4:12 PM, dan tan wrote: > Add qtest cases to exercise main TPM locality functionality > The TPM device emulation is provided by swtpm, which is TCG > TPM 2.0, and TCG TPM TIS compliant. See > https://trustedcomputinggroup.org/wp-content/uploads/TCG_PC_Client_Platform_TPM_Profile_PTP_2.0_r1.03_v22.pdf > https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClientTPMInterfaceSpecification_TIS__1-3_27_03212013.pdf > The SPI registers are specific to the PowerNV platform > architecture > > Signed-off-by: dan tan > --- ; > + > +static inline void tpm_reg_writeb(const PnvChip *c, > + int locl, > + uint8_t reg, > + uint8_t val) > +{ > + uint32_t tpm_reg_locl = SPI_TPM_TIS_ADDR | (locl << TPM_TIS_LOCALITY_SHIFT); > + > + spi_access_start(c, false, 1, TPM_WRITE_OP, tpm_reg_locl | reg); > + spi_write_reg(c, bswap64(val)); spi_write_reg(c, (uint64_t)val << 56); A #define for the 56 would be good. > + > +static void spi_access_start(const PnvChip *chip, > + bool n2, > + uint8_t bytes, > + uint8_t tpm_op, > + uint32_t tpm_reg) > +{ > + uint64_t cfg_reg; > + uint64_t reg_op; > + uint64_t seq_op = SEQ_OP_REG_BASIC; > + > + cfg_reg = pnv_spi_tpm_read(chip, SPI_CLK_CFG_REG); > + if (cfg_reg != CFG_COUNT_COMPARE_1) { > + pnv_spi_tpm_write(chip, SPI_CLK_CFG_REG, CFG_COUNT_COMPARE_1); > + } > + /* bytes - sequencer operation register bits 24:31 */ > + if (n2) { > + seq_op |= SPI_SHIFT_COUNTER_N2 | (bytes << 0x18); > + } else { > + seq_op |= SPI_SHIFT_COUNTER_N1 | (bytes << 0x18); > + } > + pnv_spi_tpm_write(chip, SPI_SEQ_OP_REG, seq_op); > + pnv_spi_tpm_write(chip, SPI_MM_REG, MM_REG_RDR_MATCH); > + pnv_spi_tpm_write(chip, SPI_CTR_CFG_REG, (uint64_t)0); > + reg_op = bswap64(tpm_op) | ((uint64_t)tpm_reg << 0x20); Same #define to use here, maybe called SPI_XMIT_DATA_OP_SHIFT. And one for the 0x20, maybe called SPI_XMIT_DATA_ADDR_SHIFT. Any reference to a spec? (uint64_t)tmp_op << SPI_XMIT_DATA_OP_SHIFT | (uint64_t)(tpm_reg & 0xffffff) << SPI_XMIT_DATA_ADDR_SHIFT; > + pnv_spi_tpm_write(chip, SPI_XMIT_DATA_REG, reg_op); > +} > +