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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Anton Johansson <anjo@rev.ng>, qemu-devel@nongnu.org
Cc: pierrick.bouvier@linaro.org, alistair.francis@wdc.com,
	palmer@dabbelt.com
Subject: Re: [PATCH v3 29/34] target/riscv: Fix size of trigger data
Date: Wed, 15 Oct 2025 22:51:37 +0200	[thread overview]
Message-ID: <3395a80a-d3db-4ebd-a11c-e7746d59c9ce@linaro.org> (raw)
In-Reply-To: <20251014203512.26282-30-anjo@rev.ng>

On 14/10/25 22:35, Anton Johansson wrote:
> mcontext is at most 14 bits in size with the H extension, fix to 16
> bits. trigger_cur indexes into tdata*[RV_MAX_TRIGGERS] which holds 2
> elements, fix to 8 bits.
> 
> Note, the cpu/debug VMSTATE version is bumped, breaking migration from
> older versions.
> 
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
> ---
>   target/riscv/cpu.h     | 10 +++++-----
>   target/riscv/machine.c | 12 ++++++------
>   2 files changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 85ad250a8f..e404b120bc 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -466,11 +466,11 @@ struct CPUArchState {
>       target_ulong mseccfg;
>   
>       /* trigger module */
> -    target_ulong trigger_cur;
> -    target_ulong tdata1[RV_MAX_TRIGGERS];
> -    target_ulong tdata2[RV_MAX_TRIGGERS];
> -    target_ulong tdata3[RV_MAX_TRIGGERS];
> -    target_ulong mcontext;
> +    uint16_t mcontext;
> +    uint8_t trigger_cur;
> +    uint64_t tdata1[RV_MAX_TRIGGERS];
> +    uint64_t tdata2[RV_MAX_TRIGGERS];
> +    uint64_t tdata3[RV_MAX_TRIGGERS];
>       struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS];
>       struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS];
>       QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS];
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 376075b2bd..e86fc58e43 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -239,15 +239,15 @@ static int debug_post_load(void *opaque, int version_id)
>   
>   static const VMStateDescription vmstate_debug = {
>       .name = "cpu/debug",
> -    .version_id = 2,
> -    .minimum_version_id = 2,
> +    .version_id = 3,
> +    .minimum_version_id = 3,
>       .needed = debug_needed,
>       .post_load = debug_post_load,
>       .fields = (const VMStateField[]) {
> -        VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
> -        VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS),
> -        VMSTATE_UINTTL_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS),
> -        VMSTATE_UINTTL_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS),
> +        VMSTATE_UINT8(env.trigger_cur, RISCVCPU),
> +        VMSTATE_UINT64_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS),
> +        VMSTATE_UINT64_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS),
> +        VMSTATE_UINT64_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS),

Pre-existing, but mcontext is not migrated. Deliberate?

Otherwise:
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

>           VMSTATE_END_OF_LIST()
>       }
>   };



  reply	other threads:[~2025-10-15 20:52 UTC|newest]

Thread overview: 65+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-14 20:34 [PATCH v3 00/34] single-binary: Make riscv cpu.h target independent Anton Johansson via
2025-10-14 20:34 ` [PATCH v3 01/34] target/riscv: Use 32 bits for misa extensions Anton Johansson via
2025-10-14 20:34 ` [PATCH v3 02/34] target/riscv: Fix size of trivial CPUArchState fields Anton Johansson via
2025-10-14 20:34 ` [PATCH v3 03/34] target/riscv: Fix size of mhartid Anton Johansson via
2025-10-16  3:56   ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 04/34] target/riscv: Bugfix riscv_pmu_ctr_get_fixed_counters_val() Anton Johansson via
2025-10-15 18:14   ` Pierrick Bouvier
2025-10-16  3:22     ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 05/34] target/riscv: Bugfix make bit 62 read-only 0 for sireg* cfg CSR read Anton Johansson via
2025-10-15 19:12   ` Pierrick Bouvier
2025-10-16  3:05   ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 06/34] target/riscv: Combine mhpmevent and mhpmeventh Anton Johansson via
2025-10-14 20:34 ` [PATCH v3 07/34] target/riscv: Combine mcyclecfg and mcyclecfgh Anton Johansson via
2025-10-14 20:34 ` [PATCH v3 08/34] target/riscv: Combine minstretcfg and minstretcfgh Anton Johansson via
2025-10-14 20:34 ` [PATCH v3 09/34] target/riscv: Combine mhpmcounter and mhpmcounterh Anton Johansson via
2025-10-16  4:09   ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 10/34] target/riscv: Fix size of gpr and gprh Anton Johansson via
2025-10-15 19:13   ` Pierrick Bouvier
2025-10-16  4:32   ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 11/34] target/riscv: Fix size of vector CSRs Anton Johansson via
2025-10-14 20:34 ` [PATCH v3 12/34] target/riscv: Fix size of pc, load_[val|res] Anton Johansson via
2025-10-16  4:33   ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 13/34] target/riscv: Fix size of frm and fflags Anton Johansson via
2025-10-16  4:34   ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 14/34] target/riscv: Fix size of badaddr and bins Anton Johansson via
2025-10-16  4:35   ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 15/34] target/riscv: Fix size of guest_phys_fault_addr Anton Johansson via
2025-10-16  4:50   ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 16/34] target/riscv: Fix size of priv_ver and vext_ver Anton Johansson via
2025-10-16 23:45   ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 17/34] target/riscv: Fix size of retxh Anton Johansson via
2025-10-16  5:11   ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 18/34] target/riscv: Fix size of ssp Anton Johansson via
2025-10-16  5:35   ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 19/34] target/riscv: Fix size of excp_uw2 Anton Johansson via
2025-10-15 20:53   ` Philippe Mathieu-Daudé
2025-10-16  5:35   ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 20/34] target/riscv: Fix size of sw_check_code Anton Johansson via
2025-10-15 20:52   ` Philippe Mathieu-Daudé
2025-10-16 23:14   ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 21/34] target/riscv: Fix size of priv Anton Johansson via
2025-10-16 23:00   ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 22/34] target/riscv: Fix size of gei fields Anton Johansson via
2025-10-16 23:15   ` Alistair Francis
2025-10-14 20:35 ` [PATCH v3 23/34] target/riscv: Fix size of [m|s|vs]iselect fields Anton Johansson via
2025-10-14 20:35 ` [PATCH v3 24/34] target/riscv: Fix arguments to board IMSIC emulation callbacks Anton Johansson via
2025-10-14 20:35 ` [PATCH v3 25/34] target/riscv: Fix size of irq_overflow_left Anton Johansson via
2025-10-15 20:45   ` Philippe Mathieu-Daudé
2025-10-14 20:35 ` [PATCH v3 26/34] target/riscv: Indent PMUFixedCtrState correctly Anton Johansson via
2025-10-16 23:16   ` Alistair Francis
2025-10-14 20:35 ` [PATCH v3 27/34] target/riscv: Replace target_ulong in riscv_cpu_get_trap_name() Anton Johansson via
2025-10-14 20:35 ` [PATCH v3 28/34] target/riscv: Replace target_ulong in riscv_ctr_add_entry() Anton Johansson via
2025-10-14 20:35 ` [PATCH v3 29/34] target/riscv: Fix size of trigger data Anton Johansson via
2025-10-15 20:51   ` Philippe Mathieu-Daudé [this message]
2025-10-14 20:35 ` [PATCH v3 30/34] target/riscv: Fix size of mseccfg Anton Johansson via
2025-10-14 20:35 ` [PATCH v3 31/34] target/riscv: Move debug.h include away from cpu.h Anton Johansson via
2025-10-15 20:47   ` Philippe Mathieu-Daudé
2025-10-16 23:18   ` Alistair Francis
2025-10-14 20:35 ` [PATCH v3 32/34] target/riscv: Move CSR declarations to separate csr.h header Anton Johansson via
2025-10-15 20:49   ` Philippe Mathieu-Daudé
2025-10-14 20:35 ` [PATCH v3 33/34] target/riscv: Introduce externally facing CSR access functions Anton Johansson via
2025-10-14 20:35 ` [PATCH v3 34/34] target/riscv: Make pmp.h target_ulong agnostic Anton Johansson via
2025-10-16 23:40   ` Alistair Francis
2025-10-15 20:58 ` [PATCH v3 00/34] single-binary: Make riscv cpu.h target independent Philippe Mathieu-Daudé
2025-10-16  3:30 ` Alistair Francis

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