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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-426ce583664sm31002575f8f.22.2025.10.15.13.51.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 15 Oct 2025 13:51:38 -0700 (PDT) Message-ID: <3395a80a-d3db-4ebd-a11c-e7746d59c9ce@linaro.org> Date: Wed, 15 Oct 2025 22:51:37 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 29/34] target/riscv: Fix size of trigger data Content-Language: en-US To: Anton Johansson , qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, alistair.francis@wdc.com, palmer@dabbelt.com References: <20251014203512.26282-1-anjo@rev.ng> <20251014203512.26282-30-anjo@rev.ng> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20251014203512.26282-30-anjo@rev.ng> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 14/10/25 22:35, Anton Johansson wrote: > mcontext is at most 14 bits in size with the H extension, fix to 16 > bits. trigger_cur indexes into tdata*[RV_MAX_TRIGGERS] which holds 2 > elements, fix to 8 bits. > > Note, the cpu/debug VMSTATE version is bumped, breaking migration from > older versions. > > Signed-off-by: Anton Johansson > Reviewed-by: Pierrick Bouvier > --- > target/riscv/cpu.h | 10 +++++----- > target/riscv/machine.c | 12 ++++++------ > 2 files changed, 11 insertions(+), 11 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 85ad250a8f..e404b120bc 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -466,11 +466,11 @@ struct CPUArchState { > target_ulong mseccfg; > > /* trigger module */ > - target_ulong trigger_cur; > - target_ulong tdata1[RV_MAX_TRIGGERS]; > - target_ulong tdata2[RV_MAX_TRIGGERS]; > - target_ulong tdata3[RV_MAX_TRIGGERS]; > - target_ulong mcontext; > + uint16_t mcontext; > + uint8_t trigger_cur; > + uint64_t tdata1[RV_MAX_TRIGGERS]; > + uint64_t tdata2[RV_MAX_TRIGGERS]; > + uint64_t tdata3[RV_MAX_TRIGGERS]; > struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; > struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; > QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; > diff --git a/target/riscv/machine.c b/target/riscv/machine.c > index 376075b2bd..e86fc58e43 100644 > --- a/target/riscv/machine.c > +++ b/target/riscv/machine.c > @@ -239,15 +239,15 @@ static int debug_post_load(void *opaque, int version_id) > > static const VMStateDescription vmstate_debug = { > .name = "cpu/debug", > - .version_id = 2, > - .minimum_version_id = 2, > + .version_id = 3, > + .minimum_version_id = 3, > .needed = debug_needed, > .post_load = debug_post_load, > .fields = (const VMStateField[]) { > - VMSTATE_UINTTL(env.trigger_cur, RISCVCPU), > - VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS), > - VMSTATE_UINTTL_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS), > - VMSTATE_UINTTL_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS), > + VMSTATE_UINT8(env.trigger_cur, RISCVCPU), > + VMSTATE_UINT64_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS), > + VMSTATE_UINT64_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS), > + VMSTATE_UINT64_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS), Pre-existing, but mcontext is not migrated. Deliberate? Otherwise: Reviewed-by: Philippe Mathieu-Daudé > VMSTATE_END_OF_LIST() > } > };