From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38394) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eyCqb-0003ZL-RW for qemu-devel@nongnu.org; Tue, 20 Mar 2018 04:42:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eyCqa-0007ck-JV for qemu-devel@nongnu.org; Tue, 20 Mar 2018 04:42:21 -0400 References: <1521530809-11780-1-git-send-email-zhaoshenglong@huawei.com> <1521530809-11780-3-git-send-email-zhaoshenglong@huawei.com> From: Auger Eric Message-ID: <33a7bc59-c457-03d0-90bf-ab5b2d2d46cd@redhat.com> Date: Tue, 20 Mar 2018 09:42:08 +0100 MIME-Version: 1.0 In-Reply-To: <1521530809-11780-3-git-send-email-zhaoshenglong@huawei.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 2/2] arm_gicv3_kvm: kvm_dist_get/put: skip the registers banked by GICR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Shannon Zhao , qemu-arm@nongnu.org Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org Hi Shannon, On 20/03/18 08:26, Shannon Zhao wrote: > While we skip the GIC_INTERNAL irqs, we don't change the register offset > accordingly. This will overlap the GICR registers value and leave the > last GIC_INTERNAL irq's registers out of update. > > Fix this by skipping the registers banked by GICR. > > Signed-off-by: Shannon Zhao > --- > hw/intc/arm_gicv3_kvm.c | 38 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 38 insertions(+) > > diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c > index 3536795..d423cba 100644 > --- a/hw/intc/arm_gicv3_kvm.c > +++ b/hw/intc/arm_gicv3_kvm.c > @@ -136,6 +136,12 @@ static void kvm_dist_get_priority(GICv3State *s, uint32_t offset, uint8_t *bmp) > int irq; > > field = (uint32_t *)bmp; > + /* For the KVM GICv3, affinity routing is always enabled, and the first 8 > + * GICD_IPRIORITYR registers are always RAZ/WI. The corresponding > + * functionality is replaced by GICR_IPRIORITYR. So it doesn't need to > + * sync them. > + */ > + offset += (8 * sizeof(uint32_t)); > for_each_dist_irq_reg(irq, s->num_irq, 8) { > kvm_gicd_access(s, offset, ®, false); > *field = reg; > @@ -150,6 +156,12 @@ static void kvm_dist_put_priority(GICv3State *s, uint32_t offset, uint8_t *bmp) > int irq; > > field = (uint32_t *)bmp; > + /* For the KVM GICv3, affinity routing is always enabled, and the first 8 > + * GICD_IPRIORITYR registers are always RAZ/WI. The corresponding > + * functionality is replaced by GICR_IPRIORITYR. So it doesn't need to > + * sync them. > + */ > + offset += (8 * sizeof(uint32_t)); > for_each_dist_irq_reg(irq, s->num_irq, 8) { > reg = *field; > kvm_gicd_access(s, offset, ®, true); > @@ -164,6 +176,12 @@ static void kvm_dist_get_edge_trigger(GICv3State *s, uint32_t offset, > uint32_t reg; > int irq; > > + /* For the KVM GICv3, affinity routing is always enabled, and the first 2 > + * GICD_ICFGR registers are always RAZ/WI. The corresponding > + * functionality is replaced by GICR_ICFGR. So it doesn't need to sync > + * them. > + */ > + offset += (2 * sizeof(uint32_t)); > for_each_dist_irq_reg(irq, s->num_irq, 2) { > kvm_gicd_access(s, offset, ®, false); > reg = half_unshuffle32(reg >> 1); > @@ -181,6 +199,12 @@ static void kvm_dist_put_edge_trigger(GICv3State *s, uint32_t offset, > uint32_t reg; > int irq; > > + /* For the KVM GICv3, affinity routing is always enabled, and the first 2 > + * GICD_ICFGR registers are always RAZ/WI. The corresponding > + * functionality is replaced by GICR_ICFGR. So it doesn't need to sync > + * them. > + */ > + offset += (2 * sizeof(uint32_t)); > for_each_dist_irq_reg(irq, s->num_irq, 2) { > reg = *gic_bmp_ptr32(bmp, irq); > if (irq % 32 != 0) { > @@ -222,6 +246,12 @@ static void kvm_dist_getbmp(GICv3State *s, uint32_t offset, uint32_t *bmp) > uint32_t reg; > int irq; > > + /* For the KVM GICv3, affinity routing is always enabled, and the > + * GICD_IGROUPR0/GICD_ISENABLER0/GICD_ISPENDR0/GICD_ISACTIVER0 registers > + * are always RAZ/WI. The corresponding functionality is replaced by the > + * GICR registers. So it doesn't need to sync them. > + */ > + offset += (1 * sizeof(uint32_t)); > for_each_dist_irq_reg(irq, s->num_irq, 1) { > kvm_gicd_access(s, offset, ®, false); > *gic_bmp_ptr32(bmp, irq) = reg; > @@ -235,6 +265,14 @@ static void kvm_dist_putbmp(GICv3State *s, uint32_t offset, > uint32_t reg; > int irq; > > + /* For the KVM GICv3, affinity routing is always enabled, and the > + * GICD_IGROUPR0/GICD_ISENABLER0/GICD_ISPENDR0/GICD_ISACTIVER0 registers > + * are always RAZ/WI. The corresponding functionality is replaced by the > + * GICR registers. So it doesn't need to sync them. > + */ > + offset += (1 * sizeof(uint32_t)); I wonder we couldn't create a new for_each_dist_irq_reg() macro taking the offset and clroffset and integrating that shift inside? > + if (clroffset != 0) nit style issue: brace needed here Besides Reviewed-by: Eric Auger Thanks Eric > + clroffset += (1 * sizeof(uint32_t)); > for_each_dist_irq_reg(irq, s->num_irq, 1) { > /* If this bitmap is a set/clear register pair, first write to the > * clear-reg to clear all bits before using the set-reg to write >