From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>
Subject: Re: Status of some Arm features
Date: Tue, 19 Nov 2024 08:52:43 -0800 [thread overview]
Message-ID: <33af12d7-9269-4c21-96d4-aa76becd0f09@linaro.org> (raw)
In-Reply-To: <CAFEAcA_eL+F572fZpFW2+Tz6xx5Mx5ux-axe3HR_fEf43_GLRA@mail.gmail.com>
On 11/19/24 02:09, Peter Maydell wrote:
> On Mon, 18 Nov 2024 at 23:33, Pierrick Bouvier
> <pierrick.bouvier@linaro.org> wrote:
>> I'm currently reviewing the QEMU Arm documentation, and I have a
>> question about the status of following features:
>>
>> 8.0:
>> - FEAT_DoubleLock, Double Lock
>
> This is actually an "anti-feature" :-) It is optional from v8.0
> and it must not be implemented from v9.0. We implement the handling
> of it based on the DOUBLELOCK fields in ID_AA64DFR0 and DBGDEVID
> (so it does the right thing on older named CPU types) and don't
> advertise it in "max".
>
Despite this singularity on versions implementation, should we list that
in our documentation?
>> 8.2:
>> - FEAT_ASMv8p2, Armv8.2 changes to the A64 ISA (bfc and rev64 instructions)
>
> This isn't a feature for CPU implementations; it's a feature for
> assemblers and disassemblers, which have to recognize BFC and
> REV64 mnemonics as being ways to write special-case flavours
> of the BFM and REV instructions.
>
Reading the feature description [1] or the A-profile manual:
FEAT_ASMv8p2 introduces the BFC instruction to the A64 instruction set
as an alias of BFM. It also requires that the BFC instruction and the
A64 pseudo-instruction REV64 are implemented by assemblers.
I understand it's both introducing the BFC instructions *and also*
ensure that BFC and REV64 are implemented by assemblers.
Is my interpretation wrong?
[1]
https://developer.arm.com/documentation/109697/2024_09/Feature-descriptions/The-Armv8-2-architecture-extension
It seems to be the only feature (through all versions >= 8.0) that
describes something this way, so I'm a bit puzzled about.
>> 8.4:
>> - FEAT_CNTSC, Generic Counter Scaling (hw/timer/sse-counter.c)
>
> This is optional, and we don't implement it yet. (There's an
> open ticket for it in Linaro JIRA at
> https://linaro.atlassian.net/browse/QEMU-309 )
>
Ok. For my personal knowledge, does the implementation in
hw/timer/sse-counter.c is related to it?
> thanks
> -- PMM
Thanks,
Pierrick
next prev parent reply other threads:[~2024-11-19 16:53 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-18 23:33 Status of some Arm features Pierrick Bouvier
2024-11-19 10:09 ` Peter Maydell
2024-11-19 10:54 ` Peter Maydell
2024-11-20 23:48 ` Pierrick Bouvier
2024-11-19 16:52 ` Pierrick Bouvier [this message]
2024-11-19 17:14 ` Peter Maydell
2024-11-21 0:02 ` Pierrick Bouvier
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