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[216.180.64.156]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-724771c08f6sm8601067b3a.127.2024.11.19.08.52.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 Nov 2024 08:52:44 -0800 (PST) Message-ID: <33af12d7-9269-4c21-96d4-aa76becd0f09@linaro.org> Date: Tue, 19 Nov 2024 08:52:43 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: Status of some Arm features To: Peter Maydell Cc: "qemu-devel@nongnu.org" , =?UTF-8?Q?Alex_Benn=C3=A9e?= , Richard Henderson References: <51442716-467b-46c2-b2f7-8ffdeeca320e@linaro.org> Content-Language: en-US From: Pierrick Bouvier In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/19/24 02:09, Peter Maydell wrote: > On Mon, 18 Nov 2024 at 23:33, Pierrick Bouvier > wrote: >> I'm currently reviewing the QEMU Arm documentation, and I have a >> question about the status of following features: >> >> 8.0: >> - FEAT_DoubleLock, Double Lock > > This is actually an "anti-feature" :-) It is optional from v8.0 > and it must not be implemented from v9.0. We implement the handling > of it based on the DOUBLELOCK fields in ID_AA64DFR0 and DBGDEVID > (so it does the right thing on older named CPU types) and don't > advertise it in "max". > Despite this singularity on versions implementation, should we list that in our documentation? >> 8.2: >> - FEAT_ASMv8p2, Armv8.2 changes to the A64 ISA (bfc and rev64 instructions) > > This isn't a feature for CPU implementations; it's a feature for > assemblers and disassemblers, which have to recognize BFC and > REV64 mnemonics as being ways to write special-case flavours > of the BFM and REV instructions. > Reading the feature description [1] or the A-profile manual: FEAT_ASMv8p2 introduces the BFC instruction to the A64 instruction set as an alias of BFM. It also requires that the BFC instruction and the A64 pseudo-instruction REV64 are implemented by assemblers. I understand it's both introducing the BFC instructions *and also* ensure that BFC and REV64 are implemented by assemblers. Is my interpretation wrong? [1] https://developer.arm.com/documentation/109697/2024_09/Feature-descriptions/The-Armv8-2-architecture-extension It seems to be the only feature (through all versions >= 8.0) that describes something this way, so I'm a bit puzzled about. >> 8.4: >> - FEAT_CNTSC, Generic Counter Scaling (hw/timer/sse-counter.c) > > This is optional, and we don't implement it yet. (There's an > open ticket for it in Linaro JIRA at > https://linaro.atlassian.net/browse/QEMU-309 ) > Ok. For my personal knowledge, does the implementation in hw/timer/sse-counter.c is related to it? > thanks > -- PMM Thanks, Pierrick