* [Qemu-devel] [PATCH] x86/cpufeatures: Enable new AVX512 cpu features
@ 2017-10-17 9:34 Yang Zhong
2017-10-18 10:32 ` Paolo Bonzini
0 siblings, 1 reply; 4+ messages in thread
From: Yang Zhong @ 2017-10-17 9:34 UTC (permalink / raw)
To: qemu-devel; +Cc: pbonzini, yang.zhong
Intel IceLake cpu has added new cpu features,AVX512VBMI2/GFNI/
VAES/AVX512VNNI/AVX512BITALG/VPCLMULQDQ. Those new cpu features
need expose to guest VM.
The bit definition:
CPUID.(EAX=7,ECX=0):ECX[bit 06] AVX512VBMI2
CPUID.(EAX=7,ECX=0):ECX[bit 08] GFNI
CPUID.(EAX=7,ECX=0):ECX[bit 09] VAES
CPUID.(EAX=7,ECX=0):ECX[bit 10] VPCLMULQDQ
CPUID.(EAX=7,ECX=0):ECX[bit 11] AVX512VNNI
CPUID.(EAX=7,ECX=0):ECX[bit 12] AVX512_BITALG
The release document ref below link:
https://software.intel.com/sites/default/files/managed/c5/15/
architecture-instruction-set-extensions-programming-reference.pdf
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
---
target/i386/cpu.c | 6 +++---
target/i386/cpu.h | 6 ++++++
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 98732cd..03fb8ad 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -435,9 +435,9 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
[FEAT_7_0_ECX] = {
.feat_names = {
NULL, "avx512vbmi", "umip", "pku",
- "ospke", NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, "avx512-vpopcntdq", NULL,
+ "ospke", NULL, "avx512vbmi2", NULL,
+ "gfni", "vaes", "vpclmulqdq", "avx512vnni",
+ "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
"la57", NULL, NULL, NULL,
NULL, NULL, "rdpid", NULL,
NULL, NULL, NULL, NULL,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index b086b15..cdbf8b0 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -635,6 +635,12 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_ECX_UMIP (1U << 2)
#define CPUID_7_0_ECX_PKU (1U << 3)
#define CPUID_7_0_ECX_OSPKE (1U << 4)
+#define CPUID_7_0_ECX_VBMI2 (1U << 6) /* Additional VBMI Instrs */
+#define CPUID_7_0_ECX_GFNI (1U << 8)
+#define CPUID_7_0_ECX_VAES (1U << 9)
+#define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
+#define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
+#define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
#define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */
#define CPUID_7_0_ECX_LA57 (1U << 16)
#define CPUID_7_0_ECX_RDPID (1U << 22)
--
1.9.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [Qemu-devel] [PATCH] x86/cpufeatures: Enable new AVX512 cpu features
2017-10-17 9:34 [Qemu-devel] [PATCH] x86/cpufeatures: Enable new AVX512 cpu features Yang Zhong
@ 2017-10-18 10:32 ` Paolo Bonzini
2017-10-18 10:39 ` Zhong Yang
0 siblings, 1 reply; 4+ messages in thread
From: Paolo Bonzini @ 2017-10-18 10:32 UTC (permalink / raw)
To: Yang Zhong, qemu-devel
On 17/10/2017 11:34, Yang Zhong wrote:
> Intel IceLake cpu has added new cpu features,AVX512VBMI2/GFNI/
> VAES/AVX512VNNI/AVX512BITALG/VPCLMULQDQ. Those new cpu features
> need expose to guest VM.
>
> The bit definition:
> CPUID.(EAX=7,ECX=0):ECX[bit 06] AVX512VBMI2
> CPUID.(EAX=7,ECX=0):ECX[bit 08] GFNI
> CPUID.(EAX=7,ECX=0):ECX[bit 09] VAES
> CPUID.(EAX=7,ECX=0):ECX[bit 10] VPCLMULQDQ
> CPUID.(EAX=7,ECX=0):ECX[bit 11] AVX512VNNI
> CPUID.(EAX=7,ECX=0):ECX[bit 12] AVX512_BITALG
>
> The release document ref below link:
> https://software.intel.com/sites/default/files/managed/c5/15/
> architecture-instruction-set-extensions-programming-reference.pdf
>
> Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Have you sent the KVM part of this too? I cannot find it.
Paolo
> ---
> target/i386/cpu.c | 6 +++---
> target/i386/cpu.h | 6 ++++++
> 2 files changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 98732cd..03fb8ad 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -435,9 +435,9 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
> [FEAT_7_0_ECX] = {
> .feat_names = {
> NULL, "avx512vbmi", "umip", "pku",
> - "ospke", NULL, NULL, NULL,
> - NULL, NULL, NULL, NULL,
> - NULL, NULL, "avx512-vpopcntdq", NULL,
> + "ospke", NULL, "avx512vbmi2", NULL,
> + "gfni", "vaes", "vpclmulqdq", "avx512vnni",
> + "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
> "la57", NULL, NULL, NULL,
> NULL, NULL, "rdpid", NULL,
> NULL, NULL, NULL, NULL,
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index b086b15..cdbf8b0 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -635,6 +635,12 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
> #define CPUID_7_0_ECX_UMIP (1U << 2)
> #define CPUID_7_0_ECX_PKU (1U << 3)
> #define CPUID_7_0_ECX_OSPKE (1U << 4)
> +#define CPUID_7_0_ECX_VBMI2 (1U << 6) /* Additional VBMI Instrs */
> +#define CPUID_7_0_ECX_GFNI (1U << 8)
> +#define CPUID_7_0_ECX_VAES (1U << 9)
> +#define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
> +#define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
> +#define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
> #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */
> #define CPUID_7_0_ECX_LA57 (1U << 16)
> #define CPUID_7_0_ECX_RDPID (1U << 22)
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [Qemu-devel] [PATCH] x86/cpufeatures: Enable new AVX512 cpu features
2017-10-18 10:32 ` Paolo Bonzini
@ 2017-10-18 10:39 ` Zhong Yang
2017-10-18 10:40 ` Paolo Bonzini
0 siblings, 1 reply; 4+ messages in thread
From: Zhong Yang @ 2017-10-18 10:39 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel; +Cc: yang.zhong
On Wed, Oct 18, 2017 at 12:32:42PM +0200, Paolo Bonzini wrote:
> On 17/10/2017 11:34, Yang Zhong wrote:
> > Intel IceLake cpu has added new cpu features,AVX512VBMI2/GFNI/
> > VAES/AVX512VNNI/AVX512BITALG/VPCLMULQDQ. Those new cpu features
> > need expose to guest VM.
> >
> > The bit definition:
> > CPUID.(EAX=7,ECX=0):ECX[bit 06] AVX512VBMI2
> > CPUID.(EAX=7,ECX=0):ECX[bit 08] GFNI
> > CPUID.(EAX=7,ECX=0):ECX[bit 09] VAES
> > CPUID.(EAX=7,ECX=0):ECX[bit 10] VPCLMULQDQ
> > CPUID.(EAX=7,ECX=0):ECX[bit 11] AVX512VNNI
> > CPUID.(EAX=7,ECX=0):ECX[bit 12] AVX512_BITALG
> >
> > The release document ref below link:
> > https://software.intel.com/sites/default/files/managed/c5/15/
> > architecture-instruction-set-extensions-programming-reference.pdf
> >
> > Signed-off-by: Yang Zhong <yang.zhong@intel.com>
>
> Have you sent the KVM part of this too? I cannot find it.
>
> Paolo
>\
Paolo, Thanks for review my patch!
KVM patch is waiting for our kernel colleague to send kernel side patch,
My KVM patch has some header definition depency with kernel side.
This Qemu patch has been verified on kernel and KVM's patch in newest
kernel release.
for this case, we need wait for KVM patch merged firstly? Many thanks!
Regards,
Yang
> > ---
> > target/i386/cpu.c | 6 +++---
> > target/i386/cpu.h | 6 ++++++
> > 2 files changed, 9 insertions(+), 3 deletions(-)
> >
> > diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> > index 98732cd..03fb8ad 100644
> > --- a/target/i386/cpu.c
> > +++ b/target/i386/cpu.c
> > @@ -435,9 +435,9 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
> > [FEAT_7_0_ECX] = {
> > .feat_names = {
> > NULL, "avx512vbmi", "umip", "pku",
> > - "ospke", NULL, NULL, NULL,
> > - NULL, NULL, NULL, NULL,
> > - NULL, NULL, "avx512-vpopcntdq", NULL,
> > + "ospke", NULL, "avx512vbmi2", NULL,
> > + "gfni", "vaes", "vpclmulqdq", "avx512vnni",
> > + "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
> > "la57", NULL, NULL, NULL,
> > NULL, NULL, "rdpid", NULL,
> > NULL, NULL, NULL, NULL,
> > diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> > index b086b15..cdbf8b0 100644
> > --- a/target/i386/cpu.h
> > +++ b/target/i386/cpu.h
> > @@ -635,6 +635,12 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
> > #define CPUID_7_0_ECX_UMIP (1U << 2)
> > #define CPUID_7_0_ECX_PKU (1U << 3)
> > #define CPUID_7_0_ECX_OSPKE (1U << 4)
> > +#define CPUID_7_0_ECX_VBMI2 (1U << 6) /* Additional VBMI Instrs */
> > +#define CPUID_7_0_ECX_GFNI (1U << 8)
> > +#define CPUID_7_0_ECX_VAES (1U << 9)
> > +#define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
> > +#define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
> > +#define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
> > #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */
> > #define CPUID_7_0_ECX_LA57 (1U << 16)
> > #define CPUID_7_0_ECX_RDPID (1U << 22)
> >
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [Qemu-devel] [PATCH] x86/cpufeatures: Enable new AVX512 cpu features
2017-10-18 10:39 ` Zhong Yang
@ 2017-10-18 10:40 ` Paolo Bonzini
0 siblings, 0 replies; 4+ messages in thread
From: Paolo Bonzini @ 2017-10-18 10:40 UTC (permalink / raw)
To: Zhong Yang, qemu-devel
On 18/10/2017 12:39, Zhong Yang wrote:
> Paolo, Thanks for review my patch!
>
> KVM patch is waiting for our kernel colleague to send kernel side patch,
> My KVM patch has some header definition depency with kernel side.
>
> This Qemu patch has been verified on kernel and KVM's patch in newest
> kernel release.
>
> for this case, we need wait for KVM patch merged firstly? Many thanks!
No, just checking!
Thanks,
Paolo
^ permalink raw reply [flat|nested] 4+ messages in thread
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2017-10-17 9:34 [Qemu-devel] [PATCH] x86/cpufeatures: Enable new AVX512 cpu features Yang Zhong
2017-10-18 10:32 ` Paolo Bonzini
2017-10-18 10:39 ` Zhong Yang
2017-10-18 10:40 ` Paolo Bonzini
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