Re: [PATCH v6 3/4] target/arm/tcg/cpu64.c: Enable ASID2 for cpu_max

[Richard Henderson <richard.henderson@linaro.org>]

On 12/10/25 08:50, Jim MacArthur wrote:
> docs/system/arm/emulation.rst: Add ASID2
> 
> Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org>
> Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org>
> ---
>   docs/system/arm/emulation.rst | 1 +
>   target/arm/tcg/cpu64.c        | 4 ++++
>   2 files changed, 5 insertions(+)
> 

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

> diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
> index 31a5878a8f..3f30ea5a30 100644
> --- a/docs/system/arm/emulation.rst
> +++ b/docs/system/arm/emulation.rst
> @@ -24,6 +24,7 @@ the following architecture extensions:
>   - FEAT_AIE (Memory Attribute Index Enhancement)
>   - FEAT_Armv9_Crypto (Armv9 Cryptographic Extension)
>   - FEAT_ASID16 (16 bit ASID)
> +- FEAT_ASID2 (Concurrent use of two ASIDs)
>   - FEAT_ATS1A (Address Translation operations that ignore stage 1 permissions)
>   - FEAT_BBM at level 2 (Translation table break-before-make levels)
>   - FEAT_BF16 (AArch64 BFloat16 instructions)
> diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
> index 6871956382..ef4c0c8d73 100644
> --- a/target/arm/tcg/cpu64.c
> +++ b/target/arm/tcg/cpu64.c
> @@ -1334,6 +1334,10 @@ void aarch64_max_tcg_initfn(Object *obj)
>       t = FIELD_DP64(t, ID_AA64MMFR3, AIE, 1);      /* FEAT_AIE */
>       SET_IDREG(isar, ID_AA64MMFR3, t);
>   
> +    t = GET_IDREG(isar, ID_AA64MMFR4);
> +    t = FIELD_DP64(t, ID_AA64MMFR4, ASID2, 1);    /* FEAT_ASID2 */
> +    SET_IDREG(isar, ID_AA64MMFR4, t);
> +
>       t = GET_IDREG(isar, ID_AA64ZFR0);
>       t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 2);    /* FEAT_SVE2p1 */
>       t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2);       /* FEAT_SVE_PMULL128 */
>