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From: Richard Henderson <richard.henderson@linaro.org>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
	qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
	bmeng@tinylab.org, liweiwei@iscas.ac.cn,
	zhiwei_liu@linux.alibaba.com
Subject: Re: [PATCH v7 1/4] tcg: add 'size' param to probe_access_flags()
Date: Thu, 23 Feb 2023 14:06:42 -1000	[thread overview]
Message-ID: <33f91448-78bd-e5a9-f05f-c54e0c8c1c13@linaro.org> (raw)
In-Reply-To: <20230223234427.521114-2-dbarboza@ventanamicro.com>

On 2/23/23 13:44, Daniel Henrique Barboza wrote:
> probe_access_flags() as it is today uses probe_access_full(), which in
> turn uses probe_access_internal() with size = 0. probe_access_internal()
> then uses the size to call the tlb_fill() callback for the given CPU.
> This size param ('fault_size' as probe_access_internal() calls it) is
> ignored by most existing .tlb_fill callback implementations, e.g.
> arm_cpu_tlb_fill(), ppc_cpu_tlb_fill(), x86_cpu_tlb_fill() and
> mips_cpu_tlb_fill() to name a few.
> 
> But RISC-V riscv_cpu_tlb_fill() actually uses it. The 'size' parameter
> is used to check for PMP (Physical Memory Protection) access. This is
> necessary because PMP does not make any guarantees about all the bytes
> of the same page having the same permissions, i.e. the same page can
> have different PMP properties, so we're forced to make sub-page range
> checks. To allow RISC-V emulation to do a probe_acess_flags() that
> covers PMP, we need to either add a 'size' param to the existing
> probe_acess_flags() or create a new interface (e.g.
> probe_access_range_flags).
> 
> There are quite a few probe_* APIs already, so let's add a 'size' param
> to probe_access_flags() and re-use this API. This is done by open coding
> what probe_access_full() does inside probe_acess_flags() and passing the
> 'size' param to probe_acess_internal(). Existing probe_access_flags()
> callers use size = 0 to not change their current API usage. 'size' is
> asserted to enforce single page access like probe_access() already does.
> 
> No behavioral changes intended.
> 
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
>   accel/stubs/tcg-stub.c        |  2 +-
>   accel/tcg/cputlb.c            | 17 ++++++++++++++---
>   accel/tcg/user-exec.c         |  5 +++--
>   include/exec/exec-all.h       |  3 ++-
>   semihosting/uaccess.c         |  2 +-
>   target/arm/ptw.c              |  2 +-
>   target/arm/sve_helper.c       |  2 +-
>   target/s390x/tcg/mem_helper.c |  6 +++---
>   8 files changed, 26 insertions(+), 13 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

I'll change probe_access_full as well, just to keep them in sync.

> +int probe_access_flags(CPUArchState *env, target_ulong addr, int size,
>                          MMUAccessType access_type, int mmu_idx,
>                          bool nonfault, void **phost, uintptr_t retaddr)
>   {
>       CPUTLBEntryFull *full;
> +    int flags;
> +
> +    g_assert(-(addr | TARGET_PAGE_MASK) >= size);
> +
> +    flags = probe_access_internal(env, addr, size, access_type, mmu_idx,
> +                                  nonfault, phost, &full, retaddr);
>   
> -    return probe_access_full(env, addr, access_type, mmu_idx,
> -                             nonfault, phost, &full, retaddr);
> +    /* Handle clean RAM pages. */
> +    if (unlikely(flags & TLB_NOTDIRTY)) {
> +        notdirty_write(env_cpu(env), addr, 1, full, retaddr);
> +        flags &= ~TLB_NOTDIRTY;
> +    }
> +
> +    return flags;

But bypassing probe_access_full here is fine.


r~


  reply	other threads:[~2023-02-24  0:08 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-23 23:44 [PATCH v7 0/4] riscv: Add support for Zicbo[m,z,p] instructions Daniel Henrique Barboza
2023-02-23 23:44 ` [PATCH v7 1/4] tcg: add 'size' param to probe_access_flags() Daniel Henrique Barboza
2023-02-24  0:06   ` Richard Henderson [this message]
2023-02-24  0:10   ` Richard Henderson
2023-03-01 21:35     ` Palmer Dabbelt
2023-02-24  0:19   ` Richard Henderson
2023-02-24  0:23     ` Richard Henderson
2023-02-24  9:20       ` Daniel Henrique Barboza
2023-02-23 23:44 ` [PATCH v7 2/4] target/riscv: implement Zicboz extension Daniel Henrique Barboza
2023-02-24  0:06   ` Richard Henderson
2023-02-24  1:48   ` liweiwei
2023-02-23 23:44 ` [PATCH v7 3/4] target/riscv: implement Zicbom extension Daniel Henrique Barboza
2023-02-24  0:07   ` Richard Henderson
2023-02-24  2:01   ` liweiwei
2023-02-23 23:44 ` [PATCH v7 4/4] target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder Daniel Henrique Barboza
2023-02-24  2:03   ` liweiwei
2023-03-01 21:35 ` [PATCH v7 0/4] riscv: Add support for Zicbo[m,z,p] instructions Palmer Dabbelt
2023-03-01 21:44   ` Daniel Henrique Barboza

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