From: Paolo Bonzini <pbonzini@redhat.com>
To: Lara Lazier <laramglazier@gmail.com>, qemu-devel@nongnu.org
Subject: Re: [PATCH 3/4] target/i386: Added consistency checks for EFER
Date: Tue, 6 Jul 2021 18:48:24 +0200 [thread overview]
Message-ID: <33fdde6c-28ac-5f62-e47c-b8fbf4fac0b3@redhat.com> (raw)
In-Reply-To: <20210705081802.18960-4-laramglazier@gmail.com>
> EFER.SVME has to be set, and EFER[63:16], EFER[9], EFER[7:5]
> are reserved and must be zero.
My version of the manual says "any MBZ [must-be-zero] bit of EFER is
set", so that would be 7:1 (not 7:5), 9 and 63:16. In QEMU bits 13 and
15 are also unimplemented and thus must-be-zero.
On 05/07/21 10:18, Lara Lazier wrote:
> +#define MSR_EFER_RESERVED 0xffffffffffff02e0
> +
This has the same issue with 32-bit compilation, except in this case the
check *is* needed on 32-bit builds just without bits 63:32 set.
The obvious way here would be to add a #ifdef, but that's less
maintainable than the slightly ugly:
#define MSR_EFER_RESERVED ((target_ulong)(int)0xffff02e0u)
(where I was too lazy to compute the right mask for the bits I listed
above...).
Paolo
next prev parent reply other threads:[~2021-07-06 16:49 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-05 8:17 [PATCH 0/4] target/i386: Continuing fixing kvm-unit-tests for svm Lara Lazier
2021-07-05 8:17 ` [PATCH 1/4] target/i386: Added MSRPM and IOPM size check Lara Lazier
2021-07-06 16:01 ` Paolo Bonzini
2021-07-05 8:18 ` [PATCH 2/4] target/i386: Added DR6 and DR7 consistency checks Lara Lazier
2021-07-06 16:02 ` Paolo Bonzini
2021-07-05 8:18 ` [PATCH 3/4] target/i386: Added consistency checks for EFER Lara Lazier
2021-07-06 16:48 ` Paolo Bonzini [this message]
2021-07-05 8:18 ` [PATCH 4/4] target/i386: Added VMRUN consistency checks for CR3 and CR4 Lara Lazier
2021-07-06 16:52 ` Paolo Bonzini
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