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([2001:8003:c020:6900:12c1:9684:874a:fb3a]) by smtp.gmail.com with ESMTPSA id x11-20020aa784cb000000b006d9667206bdsm6801175pfn.90.2023.12.27.14.50.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 Dec 2023 14:50:30 -0800 (PST) Message-ID: <34263e7c-1419-4680-89ef-dd4fd28c1a88@linaro.org> Date: Thu, 28 Dec 2023 09:50:24 +1100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 17/35] target/arm: Always use arm_pan_enabled() when checking if PAN is enabled Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20231218113305.2511480-1-peter.maydell@linaro.org> <20231218113305.2511480-18-peter.maydell@linaro.org> From: Richard Henderson In-Reply-To: <20231218113305.2511480-18-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 12/18/23 22:32, Peter Maydell wrote: > Currently the code in target/arm/helper.c mostly checks the PAN bits > in env->pstate or env->uncached_cpsr directly when it wants to know > if PAN is enabled, because in most callsites we know whether we are > in AArch64 or AArch32. We do have an arm_pan_enabled() function, but > we only use it in a few places where the code might run in either an > AArch32 or AArch64 context. > > For FEAT_NV, when HCR_EL2.{NV,NV1} is {1,1} PAN is always disabled > even when the PSTATE.PAN bit is set, the "is PAN enabled" test > becomes more complicated. Make all places that check for PAN use > arm_pan_enabled(), so we have a place to put the FEAT_NV test. > > Signed-off-by: Peter Maydell > --- > target/arm/helper.c | 22 +++++++++++----------- > 1 file changed, 11 insertions(+), 11 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 3270fb11049..4b0e46cfaae 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -263,6 +263,15 @@ void init_cpreg_list(ARMCPU *cpu) > g_list_free(keys); > } > > +static bool arm_pan_enabled(CPUARMState *env) > +{ > + if (is_a64(env)) { > + return env->pstate & PSTATE_PAN; > + } else { > + return env->uncached_cpsr & CPSR_PAN; > + } > +} Worth splitting out helpers aa{32,64}_pan_enabled to avoid the is_a64 check when context dictates? Either way, Reviewed-by: Richard Henderson r~