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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ecf027d09sm1105318f8f.18.2024.10.18.00.02.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 18 Oct 2024 00:02:16 -0700 (PDT) Message-ID: <34909283-eff5-4ba3-bc9e-afcf8ec2b481@rivosinc.com> Date: Fri, 18 Oct 2024 09:02:15 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/8] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior To: Alistair Francis , Ved Shanbhogue Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Atish Patra , qemu-devel@nongnu.org References: <20240925115808.77874-1-cleger@rivosinc.com> <20240925115808.77874-3-cleger@rivosinc.com> <20241017182710.GA403564@vedvyas-XPS-13-9310> Content-Language: en-US From: =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=cleger@rivosinc.com; helo=mail-wm1-x32a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 18/10/2024 04:21, Alistair Francis wrote: > On Fri, Oct 18, 2024 at 4:27 AM Ved Shanbhogue wrote: >> >> Alistair Francis wrote: >>> $ grep -r sstatus.SDT | grep SRET >>> src/hypervisor.adoc:if the new privilege mode is VU, the `SRET` >>> instruction sets `vsstatus.SDT` >>> >>> What am I missing here? >> >> https://github.com/riscv/riscv-isa-manual/blob/ef2ec9dc9afd003d0dab6d5ca36db59864c8483c/src/machine.adoc?plain=1#L538 > > Ah, I thought you were quoting the spec directly. > > Makes sense. This patch misses the MDT bit clearing though. I'm > guessing that's implemented in a different patch, but it should be > pulled in here instead This is actually done in the patch that adds Smdbltrp (this on is for Ssdbltrp). Thanks, Clément > > Alistair > >> >> >> regards >> ved