From: Richard Henderson <richard.henderson@linaro.org>
To: Weiwei Li <liweiwei@iscas.ac.cn>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn,
lazyparser@gmail.com
Subject: Re: [PATCH v3 5/7] accel/tcg: Uncache the host address for instruction fetch when tlb size < 1
Date: Wed, 19 Apr 2023 07:45:07 +0200 [thread overview]
Message-ID: <34a0e33a-a7b4-dd5a-f968-5d4666abf4e3@linaro.org> (raw)
In-Reply-To: <20230419032725.29721-6-liweiwei@iscas.ac.cn>
On 4/19/23 05:27, Weiwei Li wrote:
> Fix https://gitlab.com/qemu-project/qemu/-/issues/1542.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1542
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
> ---
> accel/tcg/cputlb.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
> index e984a98dc4..efa0cb67c9 100644
> --- a/accel/tcg/cputlb.c
> +++ b/accel/tcg/cputlb.c
> @@ -1696,6 +1696,11 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr,
> if (p == NULL) {
> return -1;
> }
> +
> + if (full->lg_page_size < TARGET_PAGE_BITS) {
> + return -1;
> + }
> +
> if (hostp) {
> *hostp = p;
> }
next prev parent reply other threads:[~2023-04-19 5:45 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-19 3:27 [PATCH v3 0/7] target/riscv: Fix PMP related problem Weiwei Li
2023-04-19 3:27 ` [PATCH v3 1/7] target/riscv: Update pmp_get_tlb_size() Weiwei Li
2023-04-20 11:58 ` LIU Zhiwei
2023-04-20 12:27 ` Weiwei Li
2023-04-19 3:27 ` [PATCH v3 2/7] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp Weiwei Li
2023-04-20 13:19 ` LIU Zhiwei
2023-04-20 13:46 ` Weiwei Li
2023-04-19 3:27 ` [PATCH v3 3/7] target/riscv: Flush TLB when pmpaddr is updated Weiwei Li
2023-04-20 13:21 ` LIU Zhiwei
2023-04-19 3:27 ` [PATCH v3 4/7] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes Weiwei Li
2023-04-20 13:23 ` LIU Zhiwei
2023-04-19 3:27 ` [PATCH v3 5/7] accel/tcg: Uncache the host address for instruction fetch when tlb size < 1 Weiwei Li
2023-04-19 5:45 ` Richard Henderson [this message]
2023-04-19 3:27 ` [PATCH v3 6/7] target/riscv: Make the short cut really work in pmp_hart_has_privs Weiwei Li
2023-04-20 13:33 ` LIU Zhiwei
2023-04-20 13:53 ` Weiwei Li
2023-04-19 3:27 ` [PATCH v3 7/7] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write Weiwei Li
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