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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id w1-20020ac254a1000000b00516d264366fsm223809lfk.245.2024.04.18.05.52.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 18 Apr 2024 05:52:01 -0700 (PDT) Message-ID: <34b66166-9343-4c4e-836a-dbc605572ad3@redhat.com> Date: Thu, 18 Apr 2024 14:51:59 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v2 04/13] hw/arm/smmuv3: Translate CD and TT using stage-2 table Content-Language: en-US To: Mostafa Saleh , qemu-arm@nongnu.org, peter.maydell@linaro.org, qemu-devel@nongnu.org Cc: jean-philippe@linaro.org, alex.bennee@linaro.org, maz@kernel.org, nicolinc@nvidia.com, julien@xen.org, richard.henderson@linaro.org, marcin.juszkiewicz@linaro.org References: <20240408140818.3799590-1-smostafa@google.com> <20240408140818.3799590-5-smostafa@google.com> From: Eric Auger In-Reply-To: <20240408140818.3799590-5-smostafa@google.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.067, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Mostafa, On 4/8/24 16:08, Mostafa Saleh wrote: > According to the user manual (ARM IHI 0070 F.b), s/user manual/ARM SMMU architecture specification > In "5.2 Stream Table Entry": > [51:6] S1ContextPtr > If Config[1] == 1 (stage 2 enabled), this pointer is an IPA translated by > stage 2 and the programmed value must be within the range of the IAS. > > In "5.4.1 CD notes": > The translation table walks performed from TTB0 or TTB1 are always performed > in IPA space if stage 2 translations are enabled. > > So translate both the CD and the TTBx in this patch if nested translate the S1 context descriptor pointer and TTBx base addresses through the S2 stage (IPA -> PA) You may describe what you put in place to do the translation in the commit msg, new functions, macro, ... > translation is requested. > > Signed-off-by: Mostafa Saleh > --- > hw/arm/smmuv3.c | 49 ++++++++++++++++++++++++++++++------ > include/hw/arm/smmu-common.h | 17 +++++++++++++ > 2 files changed, 59 insertions(+), 7 deletions(-) > > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index 897f8fe085..a7cf543acc 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -337,14 +337,36 @@ static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf, > > } > > +static SMMUTranslationStatus smmuv3_do_translate(SMMUv3State *s, hwaddr addr, > + SMMUTransCfg *cfg, > + SMMUEventInfo *event, > + IOMMUAccessFlags flag, > + SMMUTLBEntry **out_entry); > /* @ssid > 0 not supported yet */ > -static int smmu_get_cd(SMMUv3State *s, STE *ste, uint32_t ssid, > - CD *buf, SMMUEventInfo *event) > +static int smmu_get_cd(SMMUv3State *s, STE *ste, SMMUTransCfg *cfg, > + uint32_t ssid, CD *buf, SMMUEventInfo *event) > { > dma_addr_t addr = STE_CTXPTR(ste); > int ret, i; > + SMMUTranslationStatus status; > + SMMUTLBEntry *entry; > > trace_smmuv3_get_cd(addr); > + > + if (cfg->stage == SMMU_NESTED) { > + CALL_FUNC_CFG_S2(cfg, status, smmuv3_do_translate, s, addr, > + cfg, event, IOMMU_RO, &entry); the fact we pass 2 times cfg looks pretty weird from a caller pov. See my comment below. do we somewhere check addr is within the proper addr range, IAS if S2, OAS if S1. This was missing for S1 but I think it is worth improving now. see 3.4.3 > + /* > + * It is not clear what should happen if this fails, so we return here > + * which gets propagated as a translation error. but the error event might be different, no? > + */ > + if (status != SMMU_TRANS_SUCCESS) { > + return -EINVAL; > + } > + > + addr = CACHED_ENTRY_TO_ADDR(entry, addr); > + } > + > /* TODO: guarantee 64-bit single-copy atomicity */ > ret = dma_memory_read(&address_space_memory, addr, buf, sizeof(*buf), > MEMTXATTRS_UNSPECIFIED); > @@ -659,10 +681,13 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, > return 0; > } > > -static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event) > +static int decode_cd(SMMUv3State *s, SMMUTransCfg *cfg, > + CD *cd, SMMUEventInfo *event) > { > int ret = -EINVAL; > int i; > + SMMUTranslationStatus status; > + SMMUTLBEntry *entry; > > if (!CD_VALID(cd) || !CD_AARCH64(cd)) { > goto bad_cd; > @@ -713,6 +738,17 @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event) > > tt->tsz = tsz; > tt->ttb = CD_TTB(cd, i); > + > + /* Translate the TTBx, from IPA to PA if nesting is enabled. */ > + if (cfg->stage == SMMU_NESTED) { > + CALL_FUNC_CFG_S2(cfg, status, smmuv3_do_translate, s, > + tt->ttb, cfg, event, IOMMU_RO, &entry); > + /* See smmu_get_cd(). */ ditto > + if (status != SMMU_TRANS_SUCCESS) { > + return -EINVAL; > + } > + tt->ttb = CACHED_ENTRY_TO_ADDR(entry, tt->ttb); > + } > if (tt->ttb & ~(MAKE_64BIT_MASK(0, cfg->oas))) { > goto bad_cd; > } > @@ -767,12 +803,12 @@ static int smmuv3_decode_config(IOMMUMemoryRegion *mr, SMMUTransCfg *cfg, > return 0; > } > > - ret = smmu_get_cd(s, &ste, 0 /* ssid */, &cd, event); > + ret = smmu_get_cd(s, &ste, cfg, 0 /* ssid */, &cd, event); > if (ret) { > return ret; > } > > - return decode_cd(cfg, &cd, event); > + return decode_cd(s, cfg, &cd, event); > } > > /** > @@ -942,8 +978,7 @@ epilogue: > switch (status) { > case SMMU_TRANS_SUCCESS: > entry.perm = cached_entry->entry.perm; > - entry.translated_addr = cached_entry->entry.translated_addr + > - (addr & cached_entry->entry.addr_mask); > + entry.translated_addr = CACHED_ENTRY_TO_ADDR(cached_entry, addr); > entry.addr_mask = cached_entry->entry.addr_mask; > trace_smmuv3_translate_success(mr->parent_obj.name, sid, addr, > entry.translated_addr, entry.perm, > diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h > index 96eb017e50..2772175115 100644 > --- a/include/hw/arm/smmu-common.h > +++ b/include/hw/arm/smmu-common.h > @@ -37,6 +37,23 @@ > #define VMSA_IDXMSK(isz, strd, lvl) ((1ULL << \ > VMSA_BIT_LVL(isz, strd, lvl)) - 1) > > +#define CACHED_ENTRY_TO_ADDR(ent, addr) (ent)->entry.translated_addr + \ > + ((addr) & (ent)->entry.addr_mask); > + > +/* > + * From nested context, some functions might need to translate IPA addresses. > + * As cfg has SMMU_NESTED, this won't work, this macro calls a function with > + * making it a stage-2 cfg and then restore it after. > + */ > +#define CALL_FUNC_CFG_S2(cfg, ret, fn, ...) ({ \ > + int asid = cfg->asid; \ > + cfg->stage = SMMU_STAGE_2; \ > + cfg->asid = -1; \ > + ret = fn(__VA_ARGS__); \ At this stage of the reading this is not obvious why you need fn() parameter, can't you simply call smmuv3_do_translate(). If this is useful at some point in the series, you shall document that in the commit msg. Also I think I would prefer a proper function instead of this macro. Besides, can't we add an extra parameter to the translate function forcing the S2_only translation although the cfg is a nested one. I think this would make things clearer > + cfg->asid = asid; \ > + cfg->stage = SMMU_NESTED; \ > + }) > + > /* > * Page table walk error types > */ Thanks Eric