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From: Laurent Vivier <lvivier@redhat.com>
Message-ID: <34c1ac48-0fe4-dd44-7dd8-c49bb0e510a3@redhat.com>
Date: Thu, 30 Nov 2017 08:54:06 +0100
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Subject: Re: [Qemu-devel] [RFC PATCH 1/1] target-ppc: Don't invalidate
 non-supported msr bits
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To: David Gibson <david@gibson.dropbear.id.au>, Kurban Mallachiev <mallachiev@ispras.ru>
Cc: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Alexander Graf <agraf@suse.de>

On 30/11/2017 04:58, David Gibson wrote:
> On Wed, Nov 29, 2017 at 07:22:19PM +0300, Kurban Mallachiev wrote:
>> The msr invalidation code (commits 993eb and 2360b) inverts all
>> bits except MSR_TGPR and MSR_HVB. On non PowerPC 601 processors
>> this leads to incorrect change of excp_prefix in hreg_store_msr()
>> function. The problem is that new msr value get multiplied by msr_mask
>> and inverted msr does not, thus values of MSR_EP bit in new msr value
>> and inverted msr are distinct, so that excp_prefix changes but should
>> not.
>>
>> Signed-off-by: Kurban Mallachiev <mallachiev@ispras.ru>
> 
> So, the whole logic of ppc_store_msr() / hreg_store_msr() looks much
> harier than it should be to me.  Nonetheless, this definitely looks
> like an improvement over the current code.
> 
> Applied to ppc-for-2.11.
> 
> Laurent, could this be related to the loadvm state problems you were
> seeing in several BZs?

Thank you David, I've tried and this doesn't solve my problems.

Laurent