From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com,
bin.meng@windriver.com, richard.henderson@linaro.org,
lzw194868@alibaba-inc.com
Subject: Re: [RFC PATCH 1/3] tcg/riscv: Fix base regsiter for qemu_ld/st
Date: Thu, 20 Oct 2022 13:26:13 +0200 [thread overview]
Message-ID: <34c3cd43-3be8-7890-108e-89bd77eedc65@linaro.org> (raw)
In-Reply-To: <20221020104154.4276-2-zhiwei_liu@linux.alibaba.com>
On 20/10/22 12:41, LIU Zhiwei wrote:
> When guest base is zero, we should use addr_regl as base regiser instead of
Typo "register" here and in patch subject.
> the initial register TCG_REG_TMP0.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> ---
> tcg/riscv/tcg-target.c.inc | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index 81a83e45b1..32f4bc7bfc 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -1185,6 +1185,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
> }
> if (guest_base != 0) {
> tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
> + } else {
> + base = addr_regl;
> }
> tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
> #endif
> @@ -1257,6 +1259,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
> }
> if (guest_base != 0) {
> tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
> + } else {
> + base = addr_regl;
> }
> tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
> #endif
Maybe worth inverting the if statement, otherwise LGTM.
next prev parent reply other threads:[~2022-10-20 14:08 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-20 10:41 [RFC PATCH 0/3] Fix some TCG RISC-V backend bugs LIU Zhiwei
2022-10-20 10:41 ` [RFC PATCH 1/3] tcg/riscv: Fix base regsiter for qemu_ld/st LIU Zhiwei
2022-10-20 11:18 ` Richard Henderson
2022-10-20 11:42 ` LIU Zhiwei
2022-10-20 11:26 ` Philippe Mathieu-Daudé [this message]
2022-10-20 11:44 ` LIU Zhiwei
2022-10-20 10:41 ` [RFC PATCH 2/3] tcg/riscv: Fix tcg_out_opc_imm when imm exceeds LIU Zhiwei
2022-10-20 11:22 ` Richard Henderson
2022-10-20 12:42 ` LIU Zhiwei
2022-10-21 2:57 ` LIU Zhiwei
2022-10-21 4:29 ` Richard Henderson
2022-10-20 10:41 ` [RFC PATCH 3/3] tcg/riscv: Remove a wrong optimization for addsub2 LIU Zhiwei
2022-10-20 11:31 ` Richard Henderson
2022-10-20 12:39 ` LIU Zhiwei
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