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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id b197-20020a6334ce000000b004da637aae96sm2928120pga.31.2023.01.27.17.47.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 27 Jan 2023 17:47:07 -0800 (PST) Message-ID: <351b2481-4e80-57db-f06c-3dbf95db06fe@linaro.org> Date: Fri, 27 Jan 2023 15:47:04 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH 06/23] target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1 Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20230127175507.2895013-1-peter.maydell@linaro.org> <20230127175507.2895013-7-peter.maydell@linaro.org> From: Richard Henderson In-Reply-To: <20230127175507.2895013-7-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.148, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/27/23 07:54, Peter Maydell wrote: > +void HELPER(hstr_trap_check)(CPUARMState *env, uint32_t mask, uint32_t syndrome) > +{ > + if (env->cp15.hstr_el2 & mask) { > + raise_exception(env, EXCP_UDEF, syndrome, 2); > + } This is so simple... > @@ -4760,6 +4761,28 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, > break; > } > > + if (s->hstr_active && cpnum == 15 && s->current_el == 1) { > + /* > + * At EL1, check for a HSTR_EL2 trap, which must take precedence > + * over the UNDEF for "no such register" or the UNDEF for "access > + * permissions forbid this EL1 access". HSTR_EL2 traps from EL0 > + * only happen if the cpreg doesn't UNDEF at EL0, so we do those in > + * access_check_cp_reg(), after the checks for whether the access > + * configurably trapped to EL1. > + */ > + uint32_t maskbit = is64 ? crm : crn; > + > + if (maskbit != 4 && maskbit != 14) { > + /* T4 and T14 are RES0 so never cause traps */ > + gen_set_condexec(s); > + gen_update_pc(s, 0); > + emitted_update_pc = true; > + gen_helper_hstr_trap_check(cpu_env, > + tcg_constant_i32(1 << maskbit), > + tcg_constant_i32(syndrome)); > + } How about if (maskbit...) { TCGv_i32 t = load_cpu_offset(offsetoflow32(CPUARMState, hstr_el2)); DisasLabel *over = gen_disas_label(s); tcg_gen_andi_i32(t, t, 1u << maskbit); tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, over.label); tcg_temp_free_i32(t); gen_exception_insn(s, 0, EXCP_UDEF, syndrome); set_disas_label(s, over); } which also eliminates the need for emitted_update_pc. r~