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Fri, 17 Oct 2025 12:03:52 -0700 (PDT) Received: from [192.168.0.4] ([71.212.157.132]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-33ba96ca5d9sm2800586a91.2.2025.10.17.12.03.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Oct 2025 12:03:51 -0700 (PDT) Message-ID: <3593bf1e-1036-485c-87c9-41fc650823b7@linaro.org> Date: Fri, 17 Oct 2025 12:03:50 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 21/37] target/arm: Extend PAR_EL1 to 128-bit To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20251014200718.422022-1-richard.henderson@linaro.org> <20251014200718.422022-22-richard.henderson@linaro.org> From: Richard Henderson Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/17/25 05:49, Peter Maydell wrote: > On Tue, 14 Oct 2025 at 21:19, Richard Henderson > wrote: >> >> Do not yet produce the 128-bit AT format result, but zero the >> high bits whenever the low bits are written. This corresponds >> to PAR_EL1.D128 = 0, and bits [127:65] as RES0. >> >> Signed-off-by: Richard Henderson > > >> diff --git a/target/arm/tcg/cpregs-at.c b/target/arm/tcg/cpregs-at.c >> index 0e8f229aa7..9e6af3d974 100644 >> --- a/target/arm/tcg/cpregs-at.c >> +++ b/target/arm/tcg/cpregs-at.c >> @@ -353,6 +353,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, >> >> ss = for_el3 ? arm_security_space(env) : arm_security_space_below_el3(env); >> env->cp15.par_el[1] = do_ats_write(env, value, access_perm, mmu_idx, ss); >> + env->cp15.par_el1_hi = 0; >> } >> >> static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, >> @@ -496,6 +497,7 @@ static void ats_s1e1a(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) >> ARMSecuritySpace ss = arm_security_space_below_el3(env); >> >> env->cp15.par_el[1] = do_ats_write(env, value, 0, mmu_idx, ss); >> + env->cp15.par_el1_hi = 0; > > I guess this is where the downside of not storing the > register as an Int128 shows up -- we have to remember > to explicitly clear the high half everywhere that we > have code that's doing an implicit-write to the 64-bit > version of the register. Yes. Thankfully, PAR_EL1 is the only 128-bit register with implicit writes. r~