From: Richard Henderson <richard.henderson@linaro.org>
To: Michael Rolnik <mrolnik@gmail.com>, qemu-devel@nongnu.org
Cc: Sarah Harris <S.E.Harris@kent.ac.uk>, rth@twiddle.net
Subject: Re: [Qemu-devel] [PATCH v21 4/7] target/avr: Add instruction translation
Date: Mon, 10 Jun 2019 13:50:02 -0700 [thread overview]
Message-ID: <35b377ca-dbad-b932-5e33-c5ae63344800@linaro.org> (raw)
In-Reply-To: <20190606193012.37715-5-mrolnik@gmail.com>
On 6/6/19 12:30 PM, Michael Rolnik wrote:
> + if ((ctx.cpc & (TARGET_PAGE_SIZE - 1)) == 0) {
> + break; /* page boundary */
> + }
This test isn't right, because this ended the TB if the *first* instruction was
located on the page boundary. It also fails to allow for a 32-bit opcode to
span 0xff - 0x101, since we did not see an instruction boundary at 0x100.
Since there is no MMU, we do not have to protect against permissions changes.
All we have to worry about is QEMU's code that detects self-modifying code.
This requires the code for each TranslationBlocks be contained within no more
than two pages. Therefore,
/* Do not allow the next insn to cross into a third code page. */
if ((ctx.npc - pc_start) * 2 >= TARGET_PAGE_SIZE - 4) {
break;
}
is the better condition. Subtracting 4 allows for the next instruction to be a
32-bit opcode. Limiting to TARGET_PAGE_SIZE allows pc_start to be located
anywhere in the first code page without allowing npc to cross into a third code
page.
r~
next prev parent reply other threads:[~2019-06-10 20:51 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-06 19:30 [Qemu-devel] [PATCH v21 0/7] QEMU AVR 8 bit cores Michael Rolnik
2019-06-06 19:30 ` [Qemu-devel] [PATCH v21 1/7] target/avr: Add outward facing interfaces and core CPU logic Michael Rolnik
2019-06-06 19:30 ` [Qemu-devel] [PATCH v21 2/7] target/avr: Add instruction helpers Michael Rolnik
2019-06-06 19:30 ` [Qemu-devel] [PATCH v21 3/7] target/avr: Add instruction decoding Michael Rolnik
2019-06-10 15:05 ` Richard Henderson
2019-06-06 19:30 ` [Qemu-devel] [PATCH v21 4/7] target/avr: Add instruction translation Michael Rolnik
2019-06-10 15:09 ` Richard Henderson
2019-06-10 20:09 ` Richard Henderson
2019-06-10 20:35 ` Richard Henderson
2019-06-10 20:50 ` Richard Henderson [this message]
2019-06-10 21:20 ` Richard Henderson
2019-06-11 20:21 ` Michael Rolnik
2019-06-11 20:47 ` Richard Henderson
2019-06-11 21:02 ` Michael Rolnik
2019-06-12 16:36 ` Richard Henderson
2019-06-06 19:30 ` [Qemu-devel] [PATCH v21 5/7] target/avr: Add limited support for USART and 16 bit timer peripherals Michael Rolnik
2019-06-06 19:30 ` [Qemu-devel] [PATCH v21 6/7] target/avr: Add example board configuration Michael Rolnik
2019-06-06 19:30 ` [Qemu-devel] [PATCH v21 7/7] target/avr: Register AVR support with the rest of QEMU, the build system, and the MAINTAINERS file Michael Rolnik
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=35b377ca-dbad-b932-5e33-c5ae63344800@linaro.org \
--to=richard.henderson@linaro.org \
--cc=S.E.Harris@kent.ac.uk \
--cc=mrolnik@gmail.com \
--cc=qemu-devel@nongnu.org \
--cc=rth@twiddle.net \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).