From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Subject: Re: [PATCH v4 152/163] tcg: Formalize tcg_out_goto_ptr
Date: Wed, 16 Apr 2025 13:45:21 -0700 [thread overview]
Message-ID: <35e94847-aa9a-49be-a9f4-6dae3000cb2c@linaro.org> (raw)
In-Reply-To: <20250415192515.232910-153-richard.henderson@linaro.org>
On 4/15/25 12:25, Richard Henderson wrote:
> Split these functions out from tcg_out_op.
> Define outop_goto_ptr generically.
> Call tcg_out_goto_ptr from tcg_reg_alloc_op.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tcg.c | 12 ++++++++++++
> tcg/aarch64/tcg-target.c.inc | 12 +++++-------
> tcg/arm/tcg-target.c.inc | 12 +++++-------
> tcg/i386/tcg-target.c.inc | 13 ++++++-------
> tcg/loongarch64/tcg-target.c.inc | 12 +++++-------
> tcg/mips/tcg-target.c.inc | 22 ++++++++++------------
> tcg/ppc/tcg-target.c.inc | 15 +++++++--------
> tcg/riscv/tcg-target.c.inc | 12 +++++-------
> tcg/s390x/tcg-target.c.inc | 15 +++++----------
> tcg/sparc64/tcg-target.c.inc | 14 ++++++--------
> tcg/tci/tcg-target.c.inc | 12 +++++-------
> 11 files changed, 71 insertions(+), 80 deletions(-)
>
> diff --git a/tcg/tcg.c b/tcg/tcg.c
> index f19f3b6a8a..05604d122a 100644
> --- a/tcg/tcg.c
> +++ b/tcg/tcg.c
> @@ -133,6 +133,7 @@ static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_long);
> static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2);
> static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg);
> static void tcg_out_goto_tb(TCGContext *s, int which);
> +static void tcg_out_goto_ptr(TCGContext *s, TCGReg dest);
> static void tcg_out_mb(TCGContext *s, unsigned bar);
> static void tcg_out_br(TCGContext *s, TCGLabel *l);
> static void tcg_out_set_carry(TCGContext *s);
> @@ -1137,6 +1138,10 @@ static const TCGOutOpUnary outop_extrl_i64_i32 = {
> };
> #endif
>
> +static const TCGOutOp outop_goto_ptr = {
> + .static_constraint = C_O0_I1(r),
> +};
> +
> /*
> * Register V as the TCGOutOp for O.
> * This verifies that V is of type T, otherwise give a nice compiler error.
> @@ -1198,6 +1203,8 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
> OUTOP(INDEX_op_subb1o, TCGOutOpAddSubCarry, outop_subbio),
> OUTOP(INDEX_op_xor, TCGOutOpBinary, outop_xor),
>
> + [INDEX_op_goto_ptr] = &outop_goto_ptr,
> +
> #if TCG_TARGET_REG_BITS == 32
> OUTOP(INDEX_op_brcond2_i32, TCGOutOpBrcond2, outop_brcond2),
> OUTOP(INDEX_op_setcond2_i32, TCGOutOpSetcond2, outop_setcond2),
> @@ -5818,6 +5825,11 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
> g_assert_not_reached();
> #endif
>
> + case INDEX_op_goto_ptr:
> + tcg_debug_assert(!const_args[0]);
> + tcg_out_goto_ptr(s, new_args[0]);
> + break;
> +
> default:
> if (def->flags & TCG_OPF_VECTOR) {
> tcg_out_vec_op(s, op->opc, type - TCG_TYPE_V64,
> diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
> index fceb6e2796..2678e1f176 100644
> --- a/tcg/aarch64/tcg-target.c.inc
> +++ b/tcg/aarch64/tcg-target.c.inc
> @@ -1986,6 +1986,11 @@ static void tcg_out_goto_tb(TCGContext *s, int which)
> tcg_out_bti(s, BTI_J);
> }
>
> +static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0)
> +{
> + tcg_out_insn(s, 3207, BR, a0);
> +}
> +
> void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
> uintptr_t jmp_rx, uintptr_t jmp_rw)
> {
> @@ -2775,10 +2780,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
> TCGArg a2 = args[2];
>
> switch (opc) {
> - case INDEX_op_goto_ptr:
> - tcg_out_insn(s, 3207, BR, a0);
> - break;
> -
> case INDEX_op_ld8u_i32:
> case INDEX_op_ld8u_i64:
> tcg_out_ldst(s, I3312_LDRB, a0, a1, a2, 0);
> @@ -3293,9 +3294,6 @@ static TCGConstraintSetIndex
> tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> {
> switch (op) {
> - case INDEX_op_goto_ptr:
> - return C_O0_I1(r);
> -
> case INDEX_op_ld8u_i32:
> case INDEX_op_ld8s_i32:
> case INDEX_op_ld16u_i32:
> diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
> index 327b01d377..64be0a7e6d 100644
> --- a/tcg/arm/tcg-target.c.inc
> +++ b/tcg/arm/tcg-target.c.inc
> @@ -1795,6 +1795,11 @@ static void tcg_out_goto_tb(TCGContext *s, int which)
> set_jmp_reset_offset(s, which);
> }
>
> +static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0)
> +{
> + tcg_out_b_reg(s, COND_AL, a0);
> +}
> +
> void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
> uintptr_t jmp_rx, uintptr_t jmp_rw)
> {
> @@ -2524,10 +2529,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> const int const_args[TCG_MAX_OP_ARGS])
> {
> switch (opc) {
> - case INDEX_op_goto_ptr:
> - tcg_out_b_reg(s, COND_AL, args[0]);
> - break;
> -
> case INDEX_op_ld8u_i32:
> tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]);
> break;
> @@ -2579,9 +2580,6 @@ static TCGConstraintSetIndex
> tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> {
> switch (op) {
> - case INDEX_op_goto_ptr:
> - return C_O0_I1(r);
> -
> case INDEX_op_ld8u_i32:
> case INDEX_op_ld8s_i32:
> case INDEX_op_ld16u_i32:
> diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
> index f89982378b..5ea4a44264 100644
> --- a/tcg/i386/tcg-target.c.inc
> +++ b/tcg/i386/tcg-target.c.inc
> @@ -2593,6 +2593,12 @@ static void tcg_out_goto_tb(TCGContext *s, int which)
> set_jmp_reset_offset(s, which);
> }
>
> +static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0)
> +{
> + /* Jump to the given host address (could be epilogue) */
> + tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, a0);
> +}
> +
> void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
> uintptr_t jmp_rx, uintptr_t jmp_rw)
> {
> @@ -3437,10 +3443,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> rexw = type == TCG_TYPE_I32 ? 0 : P_REXW;
>
> switch (opc) {
> - case INDEX_op_goto_ptr:
> - /* jmp to the given host address (could be epilogue) */
> - tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, a0);
> - break;
> OP_32_64(ld8u):
> /* Note that we can ignore REXW for the zero-extend to 64-bit. */
> tcg_out_modrm_offset(s, OPC_MOVZBL, a0, a1, a2);
> @@ -4093,9 +4095,6 @@ static TCGConstraintSetIndex
> tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> {
> switch (op) {
> - case INDEX_op_goto_ptr:
> - return C_O0_I1(r);
> -
> case INDEX_op_ld8u_i32:
> case INDEX_op_ld8u_i64:
> case INDEX_op_ld8s_i32:
> diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
> index 78d1542153..1bdce25cf4 100644
> --- a/tcg/loongarch64/tcg-target.c.inc
> +++ b/tcg/loongarch64/tcg-target.c.inc
> @@ -1295,6 +1295,11 @@ static void tcg_out_goto_tb(TCGContext *s, int which)
> set_jmp_reset_offset(s, which);
> }
>
> +static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0)
> +{
> + tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0);
> +}
> +
> void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
> uintptr_t jmp_rx, uintptr_t jmp_rw)
> {
> @@ -1911,10 +1916,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> TCGArg a3 = args[3];
>
> switch (opc) {
> - case INDEX_op_goto_ptr:
> - tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0);
> - break;
> -
> case INDEX_op_ld8s_i32:
> case INDEX_op_ld8s_i64:
> tcg_out_ldst(s, OPC_LD_B, a0, a1, a2);
> @@ -2485,9 +2486,6 @@ static TCGConstraintSetIndex
> tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> {
> switch (op) {
> - case INDEX_op_goto_ptr:
> - return C_O0_I1(r);
> -
> case INDEX_op_st8_i32:
> case INDEX_op_st8_i64:
> case INDEX_op_st16_i32:
> diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
> index f4d6ee10b9..9455a0a17b 100644
> --- a/tcg/mips/tcg-target.c.inc
> +++ b/tcg/mips/tcg-target.c.inc
> @@ -1571,6 +1571,16 @@ static void tcg_out_goto_tb(TCGContext *s, int which)
> }
> }
>
> +static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0)
> +{
> + tcg_out_opc_reg(s, OPC_JR, 0, a0, 0);
> + if (TCG_TARGET_REG_BITS == 64) {
> + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0);
> + } else {
> + tcg_out_nop(s);
> + }
> +}
> +
> void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
> uintptr_t jmp_rx, uintptr_t jmp_rw)
> {
> @@ -2277,15 +2287,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> a2 = args[2];
>
> switch (opc) {
> - case INDEX_op_goto_ptr:
> - /* jmp to the given host address (could be epilogue) */
> - tcg_out_opc_reg(s, OPC_JR, 0, a0, 0);
> - if (TCG_TARGET_REG_BITS == 64) {
> - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0);
> - } else {
> - tcg_out_nop(s);
> - }
> - break;
> case INDEX_op_ld8u_i32:
> case INDEX_op_ld8u_i64:
> i1 = OPC_LBU;
> @@ -2364,9 +2365,6 @@ static TCGConstraintSetIndex
> tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> {
> switch (op) {
> - case INDEX_op_goto_ptr:
> - return C_O0_I1(r);
> -
> case INDEX_op_ld8u_i32:
> case INDEX_op_ld8s_i32:
> case INDEX_op_ld16u_i32:
> diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
> index d88ec8d690..a2a5b1e570 100644
> --- a/tcg/ppc/tcg-target.c.inc
> +++ b/tcg/ppc/tcg-target.c.inc
> @@ -2843,6 +2843,13 @@ static void tcg_out_goto_tb(TCGContext *s, int which)
> set_jmp_reset_offset(s, which);
> }
>
> +static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0)
> +{
> + tcg_out32(s, MTSPR | RS(a0) | CTR);
> + tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0));
> + tcg_out32(s, BCCTR | BO_ALWAYS);
> +}
> +
> void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
> uintptr_t jmp_rx, uintptr_t jmp_rw)
> {
> @@ -3676,11 +3683,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> const int const_args[TCG_MAX_OP_ARGS])
> {
> switch (opc) {
> - case INDEX_op_goto_ptr:
> - tcg_out32(s, MTSPR | RS(args[0]) | CTR);
> - tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0));
> - tcg_out32(s, BCCTR | BO_ALWAYS);
> - break;
> case INDEX_op_ld8u_i32:
> case INDEX_op_ld8u_i64:
> tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
> @@ -4371,9 +4373,6 @@ static TCGConstraintSetIndex
> tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> {
> switch (op) {
> - case INDEX_op_goto_ptr:
> - return C_O0_I1(r);
> -
> case INDEX_op_ld8u_i32:
> case INDEX_op_ld8s_i32:
> case INDEX_op_ld16u_i32:
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index 5d8d8213cb..c1bfd93569 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -1915,6 +1915,11 @@ static void tcg_out_goto_tb(TCGContext *s, int which)
> set_jmp_reset_offset(s, which);
> }
>
> +static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0)
> +{
> + tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0);
> +}
> +
> void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
> uintptr_t jmp_rx, uintptr_t jmp_rw)
> {
> @@ -2535,10 +2540,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> TCGArg a2 = args[2];
>
> switch (opc) {
> - case INDEX_op_goto_ptr:
> - tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0);
> - break;
> -
> case INDEX_op_ld8u_i32:
> case INDEX_op_ld8u_i64:
> tcg_out_ldst(s, OPC_LBU, a0, a1, a2);
> @@ -2824,9 +2825,6 @@ static TCGConstraintSetIndex
> tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> {
> switch (op) {
> - case INDEX_op_goto_ptr:
> - return C_O0_I1(r);
> -
> case INDEX_op_ld8u_i32:
> case INDEX_op_ld8s_i32:
> case INDEX_op_ld16u_i32:
> diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
> index cdc61de4f8..2b2e00c609 100644
> --- a/tcg/s390x/tcg-target.c.inc
> +++ b/tcg/s390x/tcg-target.c.inc
> @@ -2213,6 +2213,11 @@ static void tcg_out_goto_tb(TCGContext *s, int which)
> set_jmp_reset_offset(s, which);
> }
>
> +static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0)
> +{
> + tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, a0);
> +}
> +
> void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
> uintptr_t jmp_rx, uintptr_t jmp_rw)
> {
> @@ -3033,14 +3038,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> const TCGArg args[TCG_MAX_OP_ARGS],
> const int const_args[TCG_MAX_OP_ARGS])
> {
> - TCGArg a0;
> -
> switch (opc) {
> - case INDEX_op_goto_ptr:
> - a0 = args[0];
> - tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, a0);
> - break;
> -
> OP_32_64(ld8u):
> /* ??? LLC (RXY format) is only present with the extended-immediate
> facility, whereas LLGC is always present. */
> @@ -3567,9 +3565,6 @@ static TCGConstraintSetIndex
> tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> {
> switch (op) {
> - case INDEX_op_goto_ptr:
> - return C_O0_I1(r);
> -
> case INDEX_op_ld8u_i32:
> case INDEX_op_ld8u_i64:
> case INDEX_op_ld8s_i32:
> diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
> index e4073b7732..bb83279e2c 100644
> --- a/tcg/sparc64/tcg-target.c.inc
> +++ b/tcg/sparc64/tcg-target.c.inc
> @@ -1300,6 +1300,12 @@ static void tcg_out_goto_tb(TCGContext *s, int which)
> }
> }
>
> +static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0)
> +{
> + tcg_out_arithi(s, TCG_REG_G0, a0, 0, JMPL);
> + tcg_out_mov_delay(s, TCG_REG_TB, a0);
> +}
> +
> void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
> uintptr_t jmp_rx, uintptr_t jmp_rw)
> {
> @@ -1963,11 +1969,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> a2 = args[2];
>
> switch (opc) {
> - case INDEX_op_goto_ptr:
> - tcg_out_arithi(s, TCG_REG_G0, a0, 0, JMPL);
> - tcg_out_mov_delay(s, TCG_REG_TB, a0);
> - break;
> -
> #define OP_32_64(x) \
> glue(glue(case INDEX_op_, x), _i32): \
> glue(glue(case INDEX_op_, x), _i64)
> @@ -2034,9 +2035,6 @@ static TCGConstraintSetIndex
> tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> {
> switch (op) {
> - case INDEX_op_goto_ptr:
> - return C_O0_I1(r);
> -
> case INDEX_op_ld8u_i32:
> case INDEX_op_ld8u_i64:
> case INDEX_op_ld8s_i32:
> diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
> index 55a1a74fb6..d9cd62ed3d 100644
> --- a/tcg/tci/tcg-target.c.inc
> +++ b/tcg/tci/tcg-target.c.inc
> @@ -40,9 +40,6 @@ static TCGConstraintSetIndex
> tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> {
> switch (op) {
> - case INDEX_op_goto_ptr:
> - return C_O0_I1(r);
> -
> case INDEX_op_ld8u_i32:
> case INDEX_op_ld8s_i32:
> case INDEX_op_ld16u_i32:
> @@ -534,6 +531,11 @@ static void tcg_out_goto_tb(TCGContext *s, int which)
> set_jmp_reset_offset(s, which);
> }
>
> +static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0)
> +{
> + tcg_out_op_r(s, INDEX_op_goto_ptr, a0);
> +}
> +
> void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
> uintptr_t jmp_rx, uintptr_t jmp_rw)
> {
> @@ -1146,10 +1148,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> const int const_args[TCG_MAX_OP_ARGS])
> {
> switch (opc) {
> - case INDEX_op_goto_ptr:
> - tcg_out_op_r(s, opc, args[0]);
> - break;
> -
> CASE_32_64(ld8u)
> CASE_32_64(ld8s)
> CASE_32_64(ld16u)
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
next prev parent reply other threads:[~2025-04-16 20:46 UTC|newest]
Thread overview: 316+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-15 19:22 [PATCH v4 000/163] tcg: Convert to TCGOutOp structures Richard Henderson
2025-04-15 19:22 ` [PATCH v4 001/163] tcg: Add all_outop[] Richard Henderson
2025-04-15 19:22 ` [PATCH v4 002/163] tcg: Use extract2 for cross-word 64-bit extract on 32-bit host Richard Henderson
2025-04-15 19:22 ` [PATCH v4 003/163] tcg: Remove INDEX_op_ext{8,16,32}* Richard Henderson
2025-04-15 19:22 ` [PATCH v4 004/163] tcg: Merge INDEX_op_mov_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 005/163] tcg: Convert add to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 006/163] tcg: Merge INDEX_op_add_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 007/163] tcg: Convert and to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 008/163] tcg: Merge INDEX_op_and_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 009/163] tcg/optimize: Fold andc with immediate to and Richard Henderson
2025-04-15 19:22 ` [PATCH v4 010/163] tcg/optimize: Emit add r, r, -1 in fold_setcond_tst_pow2 Richard Henderson
2025-04-15 19:22 ` [PATCH v4 011/163] tcg: Convert andc to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 012/163] tcg: Merge INDEX_op_andc_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 013/163] tcg: Convert or to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 014/163] tcg: Merge INDEX_op_or_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 015/163] tcg/optimize: Fold orc with immediate to or Richard Henderson
2025-04-15 19:22 ` [PATCH v4 016/163] tcg: Convert orc to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 017/163] tcg: Merge INDEX_op_orc_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 018/163] tcg: Convert xor to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 019/163] tcg: Merge INDEX_op_xor_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 020/163] tcg/optimize: Fold eqv with immediate to xor Richard Henderson
2025-04-15 19:22 ` [PATCH v4 021/163] tcg: Convert eqv to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 022/163] tcg: Merge INDEX_op_eqv_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 023/163] tcg: Convert nand to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 024/163] tcg: Merge INDEX_op_nand_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 025/163] tcg/loongarch64: Do not accept constant argument to nor Richard Henderson
2025-04-15 19:22 ` [PATCH v4 026/163] tcg: Convert nor to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 027/163] tcg: Merge INDEX_op_nor_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 028/163] tcg/arm: Fix constraints for sub Richard Henderson
2025-04-15 19:23 ` [PATCH v4 029/163] tcg: Convert sub to TCGOutOpSubtract Richard Henderson
2025-04-15 21:00 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 030/163] tcg: Merge INDEX_op_sub_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 031/163] tcg: Convert neg to TCGOutOpUnary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 032/163] tcg: Merge INDEX_op_neg_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 033/163] tcg: Convert not to TCGOutOpUnary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 034/163] tcg: Merge INDEX_op_not_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 035/163] tcg: Convert mul to TCGOutOpBinary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 036/163] tcg: Merge INDEX_op_mul_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 037/163] tcg: Convert muluh to TCGOutOpBinary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 038/163] tcg: Merge INDEX_op_muluh_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 039/163] tcg: Convert mulsh to TCGOutOpBinary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 040/163] tcg: Merge INDEX_op_mulsh_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 041/163] tcg: Convert div to TCGOutOpBinary Richard Henderson
2025-04-15 21:02 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 042/163] tcg: Merge INDEX_op_div_{i32,i64} Richard Henderson
2025-04-15 21:04 ` Pierrick Bouvier
2025-04-22 15:27 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 043/163] tcg: Convert divu to TCGOutOpBinary Richard Henderson
2025-04-15 21:04 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 044/163] tcg: Merge INDEX_op_divu_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 045/163] tcg: Convert div2 to TCGOutOpDivRem Richard Henderson
2025-04-15 19:23 ` [PATCH v4 046/163] tcg: Merge INDEX_op_div2_{i32,i64} Richard Henderson
2025-04-15 21:05 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 047/163] tcg: Convert divu2 to TCGOutOpDivRem Richard Henderson
2025-04-15 21:05 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 048/163] tcg: Merge INDEX_op_divu2_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 049/163] tcg: Convert rem to TCGOutOpBinary Richard Henderson
2025-04-15 21:06 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 050/163] tcg: Merge INDEX_op_rem_{i32,i64} Richard Henderson
2025-04-15 21:06 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 051/163] tcg: Convert remu to TCGOutOpBinary Richard Henderson
2025-04-15 21:07 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 052/163] tcg: Merge INDEX_op_remu_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 053/163] tcg: Convert shl to TCGOutOpBinary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 054/163] tcg: Merge INDEX_op_shl_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 055/163] tcg: Convert shr to TCGOutOpBinary Richard Henderson
2025-04-15 21:08 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 056/163] tcg: Merge INDEX_op_shr_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 057/163] tcg: Convert sar to TCGOutOpBinary Richard Henderson
2025-04-15 21:09 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 058/163] tcg: Merge INDEX_op_sar_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 059/163] tcg: Do not require both rotr and rotl from the backend Richard Henderson
2025-04-15 21:10 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 060/163] tcg: Convert rotl, rotr to TCGOutOpBinary Richard Henderson
2025-04-15 21:10 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 061/163] tcg: Merge INDEX_op_rot{l,r}_{i32,i64} Richard Henderson
2025-04-15 21:11 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 062/163] tcg: Convert clz to TCGOutOpBinary Richard Henderson
2025-04-15 21:12 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 063/163] tcg: Merge INDEX_op_clz_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 064/163] tcg: Convert ctz to TCGOutOpBinary Richard Henderson
2025-04-15 21:13 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 065/163] tcg: Merge INDEX_op_ctz_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 066/163] tcg: Convert ctpop to TCGOutOpUnary Richard Henderson
2025-04-15 21:14 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 067/163] tcg: Merge INDEX_op_ctpop_{i32,i64} Richard Henderson
2025-04-15 21:15 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 068/163] tcg: Convert muls2 to TCGOutOpMul2 Richard Henderson
2025-04-15 21:17 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 069/163] tcg: Merge INDEX_op_muls2_{i32,i64} Richard Henderson
2025-04-15 21:17 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 070/163] tcg: Convert mulu2 to TCGOutOpMul2 Richard Henderson
2025-04-15 21:18 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 071/163] tcg: Merge INDEX_op_mulu2_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 072/163] tcg/loongarch64: Support negsetcond Richard Henderson
2025-04-15 21:19 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 073/163] tcg/mips: " Richard Henderson
2025-04-15 21:20 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 074/163] tcg/tci: " Richard Henderson
2025-04-15 21:20 ` Pierrick Bouvier
2025-04-22 15:28 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 075/163] tcg: Remove TCG_TARGET_HAS_negsetcond_{i32,i64} Richard Henderson
2025-04-22 15:35 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 076/163] tcg: Convert setcond, negsetcond to TCGOutOpSetcond Richard Henderson
2025-04-15 21:21 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 077/163] tcg: Merge INDEX_op_{neg}setcond_{i32,i64}` Richard Henderson
2025-04-15 21:22 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 078/163] tcg: Convert brcond to TCGOutOpBrcond Richard Henderson
2025-04-15 21:23 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 079/163] tcg: Merge INDEX_op_brcond_{i32,i64} Richard Henderson
2025-04-15 21:24 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 080/163] tcg: Convert movcond to TCGOutOpMovcond Richard Henderson
2025-04-15 21:25 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 081/163] tcg: Merge INDEX_op_movcond_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 082/163] tcg/ppc: Drop fallback constant loading in tcg_out_cmp Richard Henderson
2025-04-15 21:26 ` Pierrick Bouvier
2025-04-16 14:39 ` Nicholas Piggin
2025-04-16 18:57 ` Richard Henderson
2025-04-15 19:23 ` [PATCH v4 083/163] tcg/arm: Expand arguments to tcg_out_cmp2 Richard Henderson
2025-04-15 21:27 ` Pierrick Bouvier
2025-04-22 15:37 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 084/163] tcg/ppc: " Richard Henderson
2025-04-15 21:27 ` Pierrick Bouvier
2025-04-16 14:43 ` Nicholas Piggin
2025-04-22 15:37 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 085/163] tcg: Convert brcond2_i32 to TCGOutOpBrcond2 Richard Henderson
2025-04-15 21:37 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 086/163] tcg: Convert setcond2_i32 to TCGOutOpSetcond2 Richard Henderson
2025-04-15 21:39 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 087/163] tcg: Convert bswap16 to TCGOutOpBswap Richard Henderson
2025-04-15 21:40 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 088/163] tcg: Merge INDEX_op_bswap16_{i32,i64} Richard Henderson
2025-04-15 21:41 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 089/163] tcg: Convert bswap32 to TCGOutOpBswap Richard Henderson
2025-04-15 21:46 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 090/163] tcg: Merge INDEX_op_bswap32_{i32,i64} Richard Henderson
2025-04-15 21:47 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 091/163] tcg: Convert bswap64 to TCGOutOpUnary Richard Henderson
2025-04-15 21:48 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 092/163] tcg: Rename INDEX_op_bswap64_i64 to INDEX_op_bswap64 Richard Henderson
2025-04-15 21:48 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 093/163] tcg: Convert extract to TCGOutOpExtract Richard Henderson
2025-04-15 21:50 ` Pierrick Bouvier
2025-06-09 13:52 ` Andrea Bolognani
2025-06-26 16:20 ` Andrea Bolognani
2025-06-27 13:16 ` Richard Henderson
2025-06-27 14:29 ` Philippe Mathieu-Daudé
2025-06-30 12:08 ` Andrea Bolognani
2025-04-15 19:24 ` [PATCH v4 094/163] tcg: Merge INDEX_op_extract_{i32,i64} Richard Henderson
2025-04-15 21:51 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 095/163] tcg: Convert sextract to TCGOutOpExtract Richard Henderson
2025-04-15 21:55 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 096/163] tcg: Merge INDEX_op_sextract_{i32,i64} Richard Henderson
2025-04-15 21:55 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 097/163] tcg: Convert ext_i32_i64 to TCGOutOpUnary Richard Henderson
2025-04-15 21:55 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 098/163] tcg: Convert extu_i32_i64 " Richard Henderson
2025-04-15 21:56 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 099/163] tcg: Convert extrl_i64_i32 " Richard Henderson
2025-04-15 21:57 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 100/163] tcg: Convert extrh_i64_i32 " Richard Henderson
2025-04-15 21:58 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 101/163] tcg: Convert deposit to TCGOutOpDeposit Richard Henderson
2025-04-15 21:59 ` Pierrick Bouvier
2025-08-28 7:37 ` Michael Tokarev
2025-04-15 19:24 ` [PATCH v4 102/163] tcg/aarch64: Improve deposit Richard Henderson
2025-04-15 22:01 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 103/163] tcg: Merge INDEX_op_deposit_{i32,i64} Richard Henderson
2025-04-15 19:24 ` [PATCH v4 104/163] tcg: Convert extract2 to TCGOutOpExtract2 Richard Henderson
2025-04-15 22:01 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 105/163] tcg: Merge INDEX_op_extract2_{i32,i64} Richard Henderson
2025-04-15 22:02 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 106/163] tcg: Expand fallback add2 with 32-bit operations Richard Henderson
2025-04-15 22:03 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 107/163] tcg: Expand fallback sub2 " Richard Henderson
2025-04-15 22:03 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 108/163] tcg: Do not default add2/sub2_i32 for 32-bit hosts Richard Henderson
2025-04-15 22:04 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 109/163] tcg/mips: Drop support for add2/sub2 Richard Henderson
2025-04-15 22:04 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 110/163] tcg/riscv: " Richard Henderson
2025-04-15 22:05 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 111/163] tcg: Move i into each for loop in liveness_pass_1 Richard Henderson
2025-04-15 22:07 ` Pierrick Bouvier
2025-04-16 6:37 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 112/163] tcg: Sink def, nb_iargs, nb_oargs loads " Richard Henderson
2025-04-15 22:09 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 113/163] tcg: Add add/sub with carry opcodes and infrastructure Richard Henderson
2025-04-16 19:01 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 114/163] tcg: Add TCGOutOp structures for add/sub carry opcodes Richard Henderson
2025-04-16 18:56 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 115/163] tcg/optimize: Handle add/sub with " Richard Henderson
2025-04-16 19:02 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 116/163] tcg/optimize: With two const operands, prefer 0 in arg1 Richard Henderson
2025-04-16 19:03 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 117/163] tcg: Use add carry opcodes to expand add2 Richard Henderson
2025-04-16 18:57 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 118/163] tcg: Use sub carry opcodes to expand sub2 Richard Henderson
2025-04-16 18:57 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 119/163] tcg/i386: Honor carry_live in tcg_out_movi Richard Henderson
2025-04-16 18:57 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 120/163] tcg/i386: Implement add/sub carry opcodes Richard Henderson
2025-04-16 18:58 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 121/163] tcg/i386: Remove support for add2/sub2 Richard Henderson
2025-04-16 18:58 ` Pierrick Bouvier
2025-04-22 16:13 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 122/163] tcg/i386: Special case addci r, 0, 0 Richard Henderson
2025-04-16 18:59 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 123/163] tcg: Add tcg_gen_addcio_{i32,i64,tl} Richard Henderson
2025-04-16 18:59 ` Pierrick Bouvier
2025-04-22 16:13 ` Philippe Mathieu-Daudé
2025-04-22 16:30 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 124/163] target/arm: Use tcg_gen_addcio_* for ADCS Richard Henderson
2025-04-16 19:00 ` Pierrick Bouvier
2025-04-22 16:15 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 125/163] target/hppa: Use tcg_gen_addcio_i64 Richard Henderson
2025-04-16 19:05 ` Pierrick Bouvier
2025-04-22 16:17 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 126/163] target/microblaze: Use tcg_gen_addcio_i32 Richard Henderson
2025-04-16 19:05 ` Pierrick Bouvier
2025-04-22 16:28 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 127/163] target/openrisc: Use tcg_gen_addcio_* for ADDC Richard Henderson
2025-04-16 19:05 ` Pierrick Bouvier
2025-04-22 16:32 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 128/163] target/ppc: Use tcg_gen_addcio_tl for ADD and SUBF Richard Henderson
2025-04-16 14:08 ` Nicholas Piggin
2025-04-16 19:08 ` Pierrick Bouvier
2025-04-22 16:33 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 129/163] target/s390x: Use tcg_gen_addcio_i64 for op_addc64 Richard Henderson
2025-04-16 19:09 ` Pierrick Bouvier
2025-04-22 16:33 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 130/163] target/sh4: Use tcg_gen_addcio_i32 for addc Richard Henderson
2025-04-16 19:09 ` Pierrick Bouvier
2025-04-22 16:34 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 131/163] target/sparc: Use tcg_gen_addcio_tl for gen_op_addcc_int Richard Henderson
2025-04-16 19:09 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 132/163] target/tricore: Use tcg_gen_addcio_i32 for gen_addc_CC Richard Henderson
2025-04-16 19:09 ` Pierrick Bouvier
2025-04-22 16:38 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 133/163] tcg/aarch64: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:10 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 134/163] tcg/aarch64: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:13 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 135/163] tcg/arm: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:14 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 136/163] tcg/arm: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:14 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 137/163] tcg/ppc: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:14 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 138/163] tcg/ppc: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:15 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 139/163] tcg/s390x: Honor carry_live in tcg_out_movi Richard Henderson
2025-04-16 19:15 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 140/163] tcg/s390: Add TCG_CT_CONST_N32 Richard Henderson
2025-04-16 19:16 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 141/163] tcg/s390x: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:16 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 142/163] tcg/s390x: Use ADD LOGICAL WITH SIGNED IMMEDIATE Richard Henderson
2025-04-16 19:18 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 143/163] tcg/s390x: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:18 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 144/163] tcg/sparc64: Hoist tcg_cond_to_bcond lookup out of tcg_out_movcc Richard Henderson
2025-04-16 6:40 ` Philippe Mathieu-Daudé
2025-04-16 19:19 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 145/163] tcg/sparc64: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:20 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 146/163] tcg/sparc64: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:20 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 147/163] tcg/tci: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:36 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 148/163] tcg/tci: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:37 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 149/163] tcg: Remove add2/sub2 opcodes Richard Henderson
2025-04-16 19:37 ` Pierrick Bouvier
2025-04-22 16:42 ` Philippe Mathieu-Daudé
2025-04-22 17:10 ` Richard Henderson
2025-04-15 19:25 ` [PATCH v4 150/163] tcg: Formalize tcg_out_mb Richard Henderson
2025-04-16 19:38 ` Pierrick Bouvier
2025-04-22 16:44 ` Philippe Mathieu-Daudé
2025-04-15 19:25 ` [PATCH v4 151/163] tcg: Formalize tcg_out_br Richard Henderson
2025-04-16 19:38 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 152/163] tcg: Formalize tcg_out_goto_ptr Richard Henderson
2025-04-16 20:45 ` Pierrick Bouvier [this message]
2025-04-15 19:25 ` [PATCH v4 153/163] tcg: Assign TCGOP_TYPE in liveness_pass_2 Richard Henderson
2025-04-16 20:46 ` Pierrick Bouvier
2025-04-18 10:46 ` Nicholas Piggin
2025-04-21 16:28 ` Richard Henderson
2025-04-15 19:25 ` [PATCH v4 154/163] tcg: Convert ld to TCGOutOpLoad Richard Henderson
2025-04-16 20:52 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 155/163] tcg: Merge INDEX_op_ld*_{i32,i64} Richard Henderson
2025-04-16 20:53 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 156/163] tcg: Convert st to TCGOutOpStore Richard Henderson
2025-04-16 20:53 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 157/163] tcg: Merge INDEX_op_st*_{i32,i64} Richard Henderson
2025-04-16 7:05 ` Philippe Mathieu-Daudé
2025-04-16 20:53 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 158/163] tcg: Stash MemOp size in TCGOP_FLAGS Richard Henderson
2025-04-16 6:55 ` Philippe Mathieu-Daudé
2025-04-16 20:54 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 159/163] tcg: Remove INDEX_op_qemu_st8_* Richard Henderson
2025-04-16 6:55 ` Philippe Mathieu-Daudé
2025-04-16 19:24 ` Richard Henderson
2025-04-16 20:55 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 160/163] tcg: Merge INDEX_op_{ld,st}_{i32,i64,i128} Richard Henderson
2025-04-16 20:56 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 161/163] tcg: Convert qemu_ld{2} to TCGOutOpLoad{2} Richard Henderson
2025-04-16 20:57 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 162/163] tcg: Convert qemu_st{2} to TCGOutOpLdSt{2} Richard Henderson
2025-04-16 20:58 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 163/163] tcg: Remove tcg_out_op Richard Henderson
2025-04-16 19:04 ` Pierrick Bouvier
2025-04-16 13:24 ` [PATCH v4 000/163] tcg: Convert to TCGOutOp structures Nicholas Piggin
2025-04-16 23:38 ` Pierrick Bouvier
2025-04-17 0:18 ` Richard Henderson
2025-04-17 0:49 ` Pierrick Bouvier
2025-04-17 12:02 ` BALATON Zoltan
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