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Wed, 16 Apr 2025 13:45:22 -0700 (PDT) Received: from [192.168.1.87] ([38.41.223.211]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73bd22f1293sm11243033b3a.99.2025.04.16.13.45.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 16 Apr 2025 13:45:22 -0700 (PDT) Message-ID: <35e94847-aa9a-49be-a9f4-6dae3000cb2c@linaro.org> Date: Wed, 16 Apr 2025 13:45:21 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 152/163] tcg: Formalize tcg_out_goto_ptr Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org References: <20250415192515.232910-1-richard.henderson@linaro.org> <20250415192515.232910-153-richard.henderson@linaro.org> From: Pierrick Bouvier In-Reply-To: <20250415192515.232910-153-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 4/15/25 12:25, Richard Henderson wrote: > Split these functions out from tcg_out_op. > Define outop_goto_ptr generically. > Call tcg_out_goto_ptr from tcg_reg_alloc_op. > > Signed-off-by: Richard Henderson > --- > tcg/tcg.c | 12 ++++++++++++ > tcg/aarch64/tcg-target.c.inc | 12 +++++------- > tcg/arm/tcg-target.c.inc | 12 +++++------- > tcg/i386/tcg-target.c.inc | 13 ++++++------- > tcg/loongarch64/tcg-target.c.inc | 12 +++++------- > tcg/mips/tcg-target.c.inc | 22 ++++++++++------------ > tcg/ppc/tcg-target.c.inc | 15 +++++++-------- > tcg/riscv/tcg-target.c.inc | 12 +++++------- > tcg/s390x/tcg-target.c.inc | 15 +++++---------- > tcg/sparc64/tcg-target.c.inc | 14 ++++++-------- > tcg/tci/tcg-target.c.inc | 12 +++++------- > 11 files changed, 71 insertions(+), 80 deletions(-) > > diff --git a/tcg/tcg.c b/tcg/tcg.c > index f19f3b6a8a..05604d122a 100644 > --- a/tcg/tcg.c > +++ b/tcg/tcg.c > @@ -133,6 +133,7 @@ static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_long); > static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2); > static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg); > static void tcg_out_goto_tb(TCGContext *s, int which); > +static void tcg_out_goto_ptr(TCGContext *s, TCGReg dest); > static void tcg_out_mb(TCGContext *s, unsigned bar); > static void tcg_out_br(TCGContext *s, TCGLabel *l); > static void tcg_out_set_carry(TCGContext *s); > @@ -1137,6 +1138,10 @@ static const TCGOutOpUnary outop_extrl_i64_i32 = { > }; > #endif > > +static const TCGOutOp outop_goto_ptr = { > + .static_constraint = C_O0_I1(r), > +}; > + > /* > * Register V as the TCGOutOp for O. > * This verifies that V is of type T, otherwise give a nice compiler error. > @@ -1198,6 +1203,8 @@ static const TCGOutOp * const all_outop[NB_OPS] = { > OUTOP(INDEX_op_subb1o, TCGOutOpAddSubCarry, outop_subbio), > OUTOP(INDEX_op_xor, TCGOutOpBinary, outop_xor), > > + [INDEX_op_goto_ptr] = &outop_goto_ptr, > + > #if TCG_TARGET_REG_BITS == 32 > OUTOP(INDEX_op_brcond2_i32, TCGOutOpBrcond2, outop_brcond2), > OUTOP(INDEX_op_setcond2_i32, TCGOutOpSetcond2, outop_setcond2), > @@ -5818,6 +5825,11 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) > g_assert_not_reached(); > #endif > > + case INDEX_op_goto_ptr: > + tcg_debug_assert(!const_args[0]); > + tcg_out_goto_ptr(s, new_args[0]); > + break; > + > default: > if (def->flags & TCG_OPF_VECTOR) { > tcg_out_vec_op(s, op->opc, type - TCG_TYPE_V64, > diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc > index fceb6e2796..2678e1f176 100644 > --- a/tcg/aarch64/tcg-target.c.inc > +++ b/tcg/aarch64/tcg-target.c.inc > @@ -1986,6 +1986,11 @@ static void tcg_out_goto_tb(TCGContext *s, int which) > tcg_out_bti(s, BTI_J); > } > > +static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0) > +{ > + tcg_out_insn(s, 3207, BR, a0); > +} > + > void tb_target_set_jmp_target(const TranslationBlock *tb, int n, > uintptr_t jmp_rx, uintptr_t jmp_rw) > { > @@ -2775,10 +2780,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext, > TCGArg a2 = args[2]; > > switch (opc) { > - case INDEX_op_goto_ptr: > - tcg_out_insn(s, 3207, BR, a0); > - break; > - > case INDEX_op_ld8u_i32: > case INDEX_op_ld8u_i64: > tcg_out_ldst(s, I3312_LDRB, a0, a1, a2, 0); > @@ -3293,9 +3294,6 @@ static TCGConstraintSetIndex > tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) > { > switch (op) { > - case INDEX_op_goto_ptr: > - return C_O0_I1(r); > - > case INDEX_op_ld8u_i32: > case INDEX_op_ld8s_i32: > case INDEX_op_ld16u_i32: > diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc > index 327b01d377..64be0a7e6d 100644 > --- a/tcg/arm/tcg-target.c.inc > +++ b/tcg/arm/tcg-target.c.inc > @@ -1795,6 +1795,11 @@ static void tcg_out_goto_tb(TCGContext *s, int which) > set_jmp_reset_offset(s, which); > } > > +static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0) > +{ > + tcg_out_b_reg(s, COND_AL, a0); > +} > + > void tb_target_set_jmp_target(const TranslationBlock *tb, int n, > uintptr_t jmp_rx, uintptr_t jmp_rw) > { > @@ -2524,10 +2529,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > const int const_args[TCG_MAX_OP_ARGS]) > { > switch (opc) { > - case INDEX_op_goto_ptr: > - tcg_out_b_reg(s, COND_AL, args[0]); > - break; > - > case INDEX_op_ld8u_i32: > tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]); > break; > @@ -2579,9 +2580,6 @@ static TCGConstraintSetIndex > tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) > { > switch (op) { > - case INDEX_op_goto_ptr: > - return C_O0_I1(r); > - > case INDEX_op_ld8u_i32: > case INDEX_op_ld8s_i32: > case INDEX_op_ld16u_i32: > diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc > index f89982378b..5ea4a44264 100644 > --- a/tcg/i386/tcg-target.c.inc > +++ b/tcg/i386/tcg-target.c.inc > @@ -2593,6 +2593,12 @@ static void tcg_out_goto_tb(TCGContext *s, int which) > set_jmp_reset_offset(s, which); > } > > +static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0) > +{ > + /* Jump to the given host address (could be epilogue) */ > + tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, a0); > +} > + > void tb_target_set_jmp_target(const TranslationBlock *tb, int n, > uintptr_t jmp_rx, uintptr_t jmp_rw) > { > @@ -3437,10 +3443,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; > > switch (opc) { > - case INDEX_op_goto_ptr: > - /* jmp to the given host address (could be epilogue) */ > - tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, a0); > - break; > OP_32_64(ld8u): > /* Note that we can ignore REXW for the zero-extend to 64-bit. */ > tcg_out_modrm_offset(s, OPC_MOVZBL, a0, a1, a2); > @@ -4093,9 +4095,6 @@ static TCGConstraintSetIndex > tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) > { > switch (op) { > - case INDEX_op_goto_ptr: > - return C_O0_I1(r); > - > case INDEX_op_ld8u_i32: > case INDEX_op_ld8u_i64: > case INDEX_op_ld8s_i32: > diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc > index 78d1542153..1bdce25cf4 100644 > --- a/tcg/loongarch64/tcg-target.c.inc > +++ b/tcg/loongarch64/tcg-target.c.inc > @@ -1295,6 +1295,11 @@ static void tcg_out_goto_tb(TCGContext *s, int which) > set_jmp_reset_offset(s, which); > } > > +static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0) > +{ > + tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0); > +} > + > void tb_target_set_jmp_target(const TranslationBlock *tb, int n, > uintptr_t jmp_rx, uintptr_t jmp_rw) > { > @@ -1911,10 +1916,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > TCGArg a3 = args[3]; > > switch (opc) { > - case INDEX_op_goto_ptr: > - tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0); > - break; > - > case INDEX_op_ld8s_i32: > case INDEX_op_ld8s_i64: > tcg_out_ldst(s, OPC_LD_B, a0, a1, a2); > @@ -2485,9 +2486,6 @@ static TCGConstraintSetIndex > tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) > { > switch (op) { > - case INDEX_op_goto_ptr: > - return C_O0_I1(r); > - > case INDEX_op_st8_i32: > case INDEX_op_st8_i64: > case INDEX_op_st16_i32: > diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc > index f4d6ee10b9..9455a0a17b 100644 > --- a/tcg/mips/tcg-target.c.inc > +++ b/tcg/mips/tcg-target.c.inc > @@ -1571,6 +1571,16 @@ static void tcg_out_goto_tb(TCGContext *s, int which) > } > } > > +static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0) > +{ > + tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); > + if (TCG_TARGET_REG_BITS == 64) { > + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); > + } else { > + tcg_out_nop(s); > + } > +} > + > void tb_target_set_jmp_target(const TranslationBlock *tb, int n, > uintptr_t jmp_rx, uintptr_t jmp_rw) > { > @@ -2277,15 +2287,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > a2 = args[2]; > > switch (opc) { > - case INDEX_op_goto_ptr: > - /* jmp to the given host address (could be epilogue) */ > - tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); > - if (TCG_TARGET_REG_BITS == 64) { > - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); > - } else { > - tcg_out_nop(s); > - } > - break; > case INDEX_op_ld8u_i32: > case INDEX_op_ld8u_i64: > i1 = OPC_LBU; > @@ -2364,9 +2365,6 @@ static TCGConstraintSetIndex > tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) > { > switch (op) { > - case INDEX_op_goto_ptr: > - return C_O0_I1(r); > - > case INDEX_op_ld8u_i32: > case INDEX_op_ld8s_i32: > case INDEX_op_ld16u_i32: > diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc > index d88ec8d690..a2a5b1e570 100644 > --- a/tcg/ppc/tcg-target.c.inc > +++ b/tcg/ppc/tcg-target.c.inc > @@ -2843,6 +2843,13 @@ static void tcg_out_goto_tb(TCGContext *s, int which) > set_jmp_reset_offset(s, which); > } > > +static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0) > +{ > + tcg_out32(s, MTSPR | RS(a0) | CTR); > + tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0)); > + tcg_out32(s, BCCTR | BO_ALWAYS); > +} > + > void tb_target_set_jmp_target(const TranslationBlock *tb, int n, > uintptr_t jmp_rx, uintptr_t jmp_rw) > { > @@ -3676,11 +3683,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > const int const_args[TCG_MAX_OP_ARGS]) > { > switch (opc) { > - case INDEX_op_goto_ptr: > - tcg_out32(s, MTSPR | RS(args[0]) | CTR); > - tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0)); > - tcg_out32(s, BCCTR | BO_ALWAYS); > - break; > case INDEX_op_ld8u_i32: > case INDEX_op_ld8u_i64: > tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]); > @@ -4371,9 +4373,6 @@ static TCGConstraintSetIndex > tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) > { > switch (op) { > - case INDEX_op_goto_ptr: > - return C_O0_I1(r); > - > case INDEX_op_ld8u_i32: > case INDEX_op_ld8s_i32: > case INDEX_op_ld16u_i32: > diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc > index 5d8d8213cb..c1bfd93569 100644 > --- a/tcg/riscv/tcg-target.c.inc > +++ b/tcg/riscv/tcg-target.c.inc > @@ -1915,6 +1915,11 @@ static void tcg_out_goto_tb(TCGContext *s, int which) > set_jmp_reset_offset(s, which); > } > > +static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0) > +{ > + tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0); > +} > + > void tb_target_set_jmp_target(const TranslationBlock *tb, int n, > uintptr_t jmp_rx, uintptr_t jmp_rw) > { > @@ -2535,10 +2540,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > TCGArg a2 = args[2]; > > switch (opc) { > - case INDEX_op_goto_ptr: > - tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0); > - break; > - > case INDEX_op_ld8u_i32: > case INDEX_op_ld8u_i64: > tcg_out_ldst(s, OPC_LBU, a0, a1, a2); > @@ -2824,9 +2825,6 @@ static TCGConstraintSetIndex > tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) > { > switch (op) { > - case INDEX_op_goto_ptr: > - return C_O0_I1(r); > - > case INDEX_op_ld8u_i32: > case INDEX_op_ld8s_i32: > case INDEX_op_ld16u_i32: > diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc > index cdc61de4f8..2b2e00c609 100644 > --- a/tcg/s390x/tcg-target.c.inc > +++ b/tcg/s390x/tcg-target.c.inc > @@ -2213,6 +2213,11 @@ static void tcg_out_goto_tb(TCGContext *s, int which) > set_jmp_reset_offset(s, which); > } > > +static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0) > +{ > + tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, a0); > +} > + > void tb_target_set_jmp_target(const TranslationBlock *tb, int n, > uintptr_t jmp_rx, uintptr_t jmp_rw) > { > @@ -3033,14 +3038,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > const TCGArg args[TCG_MAX_OP_ARGS], > const int const_args[TCG_MAX_OP_ARGS]) > { > - TCGArg a0; > - > switch (opc) { > - case INDEX_op_goto_ptr: > - a0 = args[0]; > - tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, a0); > - break; > - > OP_32_64(ld8u): > /* ??? LLC (RXY format) is only present with the extended-immediate > facility, whereas LLGC is always present. */ > @@ -3567,9 +3565,6 @@ static TCGConstraintSetIndex > tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) > { > switch (op) { > - case INDEX_op_goto_ptr: > - return C_O0_I1(r); > - > case INDEX_op_ld8u_i32: > case INDEX_op_ld8u_i64: > case INDEX_op_ld8s_i32: > diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc > index e4073b7732..bb83279e2c 100644 > --- a/tcg/sparc64/tcg-target.c.inc > +++ b/tcg/sparc64/tcg-target.c.inc > @@ -1300,6 +1300,12 @@ static void tcg_out_goto_tb(TCGContext *s, int which) > } > } > > +static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0) > +{ > + tcg_out_arithi(s, TCG_REG_G0, a0, 0, JMPL); > + tcg_out_mov_delay(s, TCG_REG_TB, a0); > +} > + > void tb_target_set_jmp_target(const TranslationBlock *tb, int n, > uintptr_t jmp_rx, uintptr_t jmp_rw) > { > @@ -1963,11 +1969,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > a2 = args[2]; > > switch (opc) { > - case INDEX_op_goto_ptr: > - tcg_out_arithi(s, TCG_REG_G0, a0, 0, JMPL); > - tcg_out_mov_delay(s, TCG_REG_TB, a0); > - break; > - > #define OP_32_64(x) \ > glue(glue(case INDEX_op_, x), _i32): \ > glue(glue(case INDEX_op_, x), _i64) > @@ -2034,9 +2035,6 @@ static TCGConstraintSetIndex > tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) > { > switch (op) { > - case INDEX_op_goto_ptr: > - return C_O0_I1(r); > - > case INDEX_op_ld8u_i32: > case INDEX_op_ld8u_i64: > case INDEX_op_ld8s_i32: > diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc > index 55a1a74fb6..d9cd62ed3d 100644 > --- a/tcg/tci/tcg-target.c.inc > +++ b/tcg/tci/tcg-target.c.inc > @@ -40,9 +40,6 @@ static TCGConstraintSetIndex > tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) > { > switch (op) { > - case INDEX_op_goto_ptr: > - return C_O0_I1(r); > - > case INDEX_op_ld8u_i32: > case INDEX_op_ld8s_i32: > case INDEX_op_ld16u_i32: > @@ -534,6 +531,11 @@ static void tcg_out_goto_tb(TCGContext *s, int which) > set_jmp_reset_offset(s, which); > } > > +static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0) > +{ > + tcg_out_op_r(s, INDEX_op_goto_ptr, a0); > +} > + > void tb_target_set_jmp_target(const TranslationBlock *tb, int n, > uintptr_t jmp_rx, uintptr_t jmp_rw) > { > @@ -1146,10 +1148,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > const int const_args[TCG_MAX_OP_ARGS]) > { > switch (opc) { > - case INDEX_op_goto_ptr: > - tcg_out_op_r(s, opc, args[0]); > - break; > - > CASE_32_64(ld8u) > CASE_32_64(ld8s) > CASE_32_64(ld16u) Reviewed-by: Pierrick Bouvier