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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: brad@comstyle.com, Alistair.Francis@wdc.com, palmer@dabbelt.com,
	qemu-riscv@nongnu.org
Subject: Re: [PATCH 1/3] util/cpuinfo-riscv: Support host/cpuinfo.h for riscv
Date: Tue, 2 Jul 2024 21:55:54 +0200	[thread overview]
Message-ID: <360734c3-df2a-49cb-892a-0eb7953fa1c1@linaro.org> (raw)
In-Reply-To: <20240627180350.128575-2-richard.henderson@linaro.org>

On 27/6/24 20:03, Richard Henderson wrote:
> Move detection code out of tcg, similar to other hosts.
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   host/include/riscv/host/cpuinfo.h | 23 +++++++++
>   tcg/riscv/tcg-target.h            | 46 ++++++++---------
>   util/cpuinfo-riscv.c              | 85 +++++++++++++++++++++++++++++++
>   tcg/riscv/tcg-target.c.inc        | 84 +++---------------------------
>   util/meson.build                  |  2 +
>   5 files changed, 139 insertions(+), 101 deletions(-)
>   create mode 100644 host/include/riscv/host/cpuinfo.h
>   create mode 100644 util/cpuinfo-riscv.c


> +/* Called both as constructor and (possibly) via other constructors. */
> +unsigned __attribute__((constructor)) cpuinfo_init(void)
> +{
> +    unsigned left = CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND;
> +    unsigned info = cpuinfo;
> +
> +    if (info) {
> +        return info;
> +    }
> +
> +    /* Test for compile-time settings. */
> +#if defined(__riscv_arch_test) && defined(__riscv_zba)
> +    info |= CPUINFO_ZBA;
> +#endif
> +#if defined(__riscv_arch_test) && defined(__riscv_zbb)
> +    info |= CPUINFO_ZBB;
> +#endif
> +#if defined(__riscv_arch_test) && defined(__riscv_zicond)
> +    info |= CPUINFO_ZICOND;
> +#endif
> +    left &= ~info;
> +
> +    if (left) {
> +        struct sigaction sa_old, sa_new;
> +
> +        memset(&sa_new, 0, sizeof(sa_new));
> +        sa_new.sa_flags = SA_SIGINFO;
> +        sa_new.sa_sigaction = sigill_handler;
> +        sigaction(SIGILL, &sa_new, &sa_old);
> +
> +        if (left & CPUINFO_ZBA) {
> +            /* Probe for Zba: add.uw zero,zero,zero. */
> +            got_sigill = 0;
> +            asm volatile(".insn r 0x3b, 0, 0x04, zero, zero, zero"
> +                         : : : "memory");
> +            info |= !got_sigill * CPUINFO_ZBA;

A bit too optimized to my taste, 'if (sigill) info|=ZBA' would be 
simpler to follow. Otherwise,

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

> +            left &= ~CPUINFO_ZBA;
> +        }



  reply	other threads:[~2024-07-02 19:56 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-27 18:03 [PATCH 0/3] util: Add cpuinfo support for riscv Richard Henderson
2024-06-27 18:03 ` [PATCH 1/3] util/cpuinfo-riscv: Support host/cpuinfo.h " Richard Henderson
2024-07-02 19:55   ` Philippe Mathieu-Daudé [this message]
2024-07-02 23:04     ` Richard Henderson
2024-07-03  7:32       ` Philippe Mathieu-Daudé
2024-07-02 22:17   ` Daniel Henrique Barboza
2024-07-02 23:56   ` Alistair Francis
2024-07-03  8:46   ` LIU Zhiwei
2024-06-27 18:03 ` [PATCH 2/3] util/cpuinfo-riscv: Support OpenBSD signal frame Richard Henderson
2024-07-02 19:58   ` Philippe Mathieu-Daudé
2024-07-02 22:16   ` Daniel Henrique Barboza
2024-07-02 23:56   ` Alistair Francis
2024-06-27 18:03 ` [PATCH 3/3] util/cpuinfo-riscv: Use linux __riscv_hwprobe syscall Richard Henderson
2024-07-02 22:15   ` Daniel Henrique Barboza
2024-07-02 23:08     ` Richard Henderson
2024-07-02 23:58   ` Alistair Francis
2024-07-02 16:26 ` [PATCH 0/3] util: Add cpuinfo support for riscv Richard Henderson

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