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Tue, 02 Jul 2024 12:55:56 -0700 (PDT) Message-ID: <360734c3-df2a-49cb-892a-0eb7953fa1c1@linaro.org> Date: Tue, 2 Jul 2024 21:55:54 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/3] util/cpuinfo-riscv: Support host/cpuinfo.h for riscv To: Richard Henderson , qemu-devel@nongnu.org Cc: brad@comstyle.com, Alistair.Francis@wdc.com, palmer@dabbelt.com, qemu-riscv@nongnu.org References: <20240627180350.128575-1-richard.henderson@linaro.org> <20240627180350.128575-2-richard.henderson@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20240627180350.128575-2-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 27/6/24 20:03, Richard Henderson wrote: > Move detection code out of tcg, similar to other hosts. > > Signed-off-by: Richard Henderson > --- > host/include/riscv/host/cpuinfo.h | 23 +++++++++ > tcg/riscv/tcg-target.h | 46 ++++++++--------- > util/cpuinfo-riscv.c | 85 +++++++++++++++++++++++++++++++ > tcg/riscv/tcg-target.c.inc | 84 +++--------------------------- > util/meson.build | 2 + > 5 files changed, 139 insertions(+), 101 deletions(-) > create mode 100644 host/include/riscv/host/cpuinfo.h > create mode 100644 util/cpuinfo-riscv.c > +/* Called both as constructor and (possibly) via other constructors. */ > +unsigned __attribute__((constructor)) cpuinfo_init(void) > +{ > + unsigned left = CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND; > + unsigned info = cpuinfo; > + > + if (info) { > + return info; > + } > + > + /* Test for compile-time settings. */ > +#if defined(__riscv_arch_test) && defined(__riscv_zba) > + info |= CPUINFO_ZBA; > +#endif > +#if defined(__riscv_arch_test) && defined(__riscv_zbb) > + info |= CPUINFO_ZBB; > +#endif > +#if defined(__riscv_arch_test) && defined(__riscv_zicond) > + info |= CPUINFO_ZICOND; > +#endif > + left &= ~info; > + > + if (left) { > + struct sigaction sa_old, sa_new; > + > + memset(&sa_new, 0, sizeof(sa_new)); > + sa_new.sa_flags = SA_SIGINFO; > + sa_new.sa_sigaction = sigill_handler; > + sigaction(SIGILL, &sa_new, &sa_old); > + > + if (left & CPUINFO_ZBA) { > + /* Probe for Zba: add.uw zero,zero,zero. */ > + got_sigill = 0; > + asm volatile(".insn r 0x3b, 0, 0x04, zero, zero, zero" > + : : : "memory"); > + info |= !got_sigill * CPUINFO_ZBA; A bit too optimized to my taste, 'if (sigill) info|=ZBA' would be simpler to follow. Otherwise, Reviewed-by: Philippe Mathieu-Daudé > + left &= ~CPUINFO_ZBA; > + }