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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42f7d330b20sm34410629f8f.29.2025.12.09.21.22.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 Dec 2025 21:22:59 -0800 (PST) Message-ID: <36365615-9e43-4ce5-a1ba-e495eacb1f24@linaro.org> Date: Wed, 10 Dec 2025 06:22:58 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH 3/3] hw/openrisc: Add the OpenRISC virtual machine Content-Language: en-US To: Richard Henderson , Joel Stanley , Stafford Horne Cc: QEMU Development , "Jason A. Donenfeld" , Openrisc References: <20220527172731.1742837-1-shorne@gmail.com> <20220527172731.1742837-4-shorne@gmail.com> <8c34270f-9fdc-3e94-0984-29d9a5e5542f@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <8c34270f-9fdc-3e94-0984-29d9a5e5542f@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/6/22 17:49, Richard Henderson wrote: > On 6/2/22 04:42, Joel Stanley wrote: >> Hi Stafford, >> >> On Fri, 27 May 2022 at 17:27, Stafford Horne wrote: >>> >>> This patch add the OpenRISC virtual machine 'virt' for OpenRISC.  This >>> platform allows for a convenient CI platform for toolchain, software >>> ports and the OpenRISC linux kernel port. >>> >>> Much of this has been sourced from the m68k and riscv virt platforms. >> >> It's a good idea! I did some playing around with your patch today. >> >> I'd suggest adding something to docs/system/target-openrsic.rst, >> including an example command lines. >> >>> >>> The platform provides: >>>   - OpenRISC SMP with up to 8 cpus >> >> You have this: >> >> #define VIRT_CPUS_MAX 4 >> >> I tried booting with -smp 4 and it locked up when starting userspace >> (or I stopped getting serial output?): >> >> [    0.060000] smp: Brought up 1 node, 4 CPUs >> ... >> [    0.960000] Run /init as init process >> >> Running with -smp 2 and 3 worked. It does make booting much much slower. > > target/openrisc/cpu.h is missing > > #define TCG_GUEST_DEFAULT_MO      (0) > > > to tell the JIT about the weakly ordered guest memory model, and to > enable MTTCG by default. > >> I enabled the options: >> >> CONFIG_RTC_CLASS=y >> # CONFIG_RTC_SYSTOHC is not set >> # CONFIG_RTC_NVMEM is not set >> CONFIG_RTC_DRV_GOLDFISH=y >> >> But it didn't work. It seems the goldfish rtc model doesn't handle a >> big endian guest running on my little endian host. >> >> Doing this fixes it: >> >> -    .endianness = DEVICE_NATIVE_ENDIAN, >> +    .endianness = DEVICE_HOST_ENDIAN, >> >> [    0.190000] goldfish_rtc 96005000.rtc: registered as rtc0 >> [    0.190000] goldfish_rtc 96005000.rtc: setting system clock to >> 2022-06-02T11:16:04 UTC (1654168564) >> >> But literally no other model in the tree does this, so I suspect it's >> not the right fix. > > Correct.  The model might require > >     .endianness = DEVICE_LITTLE_ENDIAN, > > if that is the actual specification, or it may simply require fixes to > handle a big-endian guest. > > All that said, if we're going to make up a new virt platform, it should > use PCI not virtio.  See the recent discussion about RISC-V virtual > machines, where they made exactly this mistake several years ago. Unfortunately this precious remark was missed :(