From: Harsh Prateek Bora <harshpb@linux.ibm.com>
To: Thomas Huth <thuth@redhat.com>,
Nicholas Piggin <npiggin@gmail.com>,
qemu-devel@nongnu.org
Cc: devel@lists.libvirt.org,
"Daniel Henrique Barboza" <danielhb413@gmail.com>,
"Cédric Le Goater" <clg@kaod.org>,
"David Gibson" <david@gibson.dropbear.id.au>,
"Eduardo Habkost" <eduardo@habkost.net>,
qemu-ppc@nongnu.org, "Markus Armbruster" <armbru@redhat.com>
Subject: Re: [PATCH v2 1/2] target/ppc/cpu-models: Rename power5+ and power7+ for new QOM naming rules
Date: Thu, 18 Jan 2024 10:32:51 +0530 [thread overview]
Message-ID: <36491191-6b6c-4c7e-bfdd-ea58bcd38789@linux.ibm.com> (raw)
In-Reply-To: <20240117141054.73841-2-thuth@redhat.com>
On 1/17/24 19:40, Thomas Huth wrote:
> The character "+" is now forbidden in QOM device names (see commit
> b447378e1217 - "Limit type names to alphanumerical and some few special
> characters"). For the "power5+" and "power7+" CPU names, there is
> currently a hack in type_name_is_valid() to still allow them for
> compatibility reasons. However, there is a much nicer solution for this:
> Simply use aliases! This way we can still support the old names without
> the need for the ugly hack in type_name_is_valid().
>
> Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
> ---
> hw/ppc/spapr_cpu_core.c | 4 ++--
> qom/object.c | 4 ----
> target/ppc/cpu-models.c | 10 ++++++----
> 3 files changed, 8 insertions(+), 10 deletions(-)
>
> diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
> index 5aa1ed474a..0c0fb3f1b0 100644
> --- a/hw/ppc/spapr_cpu_core.c
> +++ b/hw/ppc/spapr_cpu_core.c
> @@ -389,9 +389,9 @@ static const TypeInfo spapr_cpu_core_type_infos[] = {
> DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"),
> DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"),
> DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"),
> - DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"),
> + DEFINE_SPAPR_CPU_CORE_TYPE("power5p_v2.1"),
> DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"),
> - DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"),
> + DEFINE_SPAPR_CPU_CORE_TYPE("power7p_v2.1"),
> DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"),
> DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"),
> DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"),
> diff --git a/qom/object.c b/qom/object.c
> index 654e1afaf2..2c4c64d2b6 100644
> --- a/qom/object.c
> +++ b/qom/object.c
> @@ -160,10 +160,6 @@ static bool type_name_is_valid(const char *name)
>
> /* Allow some legacy names with '+' in it for compatibility reasons */
> if (name[plen] == '+') {
> - if (plen == 6 && g_str_has_prefix(name, "power")) {
> - /* Allow "power5+" and "power7+" CPU names*/
> - return true;
> - }
> if (plen >= 17 && g_str_has_prefix(name, "Sun-UltraSparc-I")) {
> /* Allow "Sun-UltraSparc-IV+" and "Sun-UltraSparc-IIIi+" */
> return true;
> diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
> index 7dbb47de64..36e465b390 100644
> --- a/target/ppc/cpu-models.c
> +++ b/target/ppc/cpu-models.c
> @@ -716,11 +716,11 @@
> "PowerPC 970MP v1.0")
> POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970,
> "PowerPC 970MP v1.1")
> - POWERPC_DEF("power5+_v2.1", CPU_POWERPC_POWER5P_v21, POWER5P,
> + POWERPC_DEF("power5p_v2.1", CPU_POWERPC_POWER5P_v21, POWER5P,
> "POWER5+ v2.1")
> POWERPC_DEF("power7_v2.3", CPU_POWERPC_POWER7_v23, POWER7,
> "POWER7 v2.3")
> - POWERPC_DEF("power7+_v2.1", CPU_POWERPC_POWER7P_v21, POWER7,
> + POWERPC_DEF("power7p_v2.1", CPU_POWERPC_POWER7P_v21, POWER7,
> "POWER7+ v2.1")
> POWERPC_DEF("power8e_v2.1", CPU_POWERPC_POWER8E_v21, POWER8,
> "POWER8E v2.1")
> @@ -902,10 +902,12 @@ PowerPCCPUAlias ppc_cpu_aliases[] = {
> { "970", "970_v2.2" },
> { "970fx", "970fx_v3.1" },
> { "970mp", "970mp_v1.1" },
> - { "power5+", "power5+_v2.1" },
> + { "power5+", "power5p_v2.1" },
> + { "power5+_v2.1", "power5p_v2.1" },
> { "power5gs", "power5+_v2.1" },
> { "power7", "power7_v2.3" },
> - { "power7+", "power7+_v2.1" },
> + { "power7+", "power7p_v2.1" },
> + { "power7+_v2.1", "power7p_v2.1" },
> { "power8e", "power8e_v2.1" },
> { "power8", "power8_v2.0" },
> { "power8nvl", "power8nvl_v1.0" },
next prev parent reply other threads:[~2024-01-18 5:03 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-17 14:10 [PATCH v2 0/2] ppc: Rename power5+ and power7+ for the new QOM naming rules Thomas Huth
2024-01-17 14:10 ` [PATCH v2 1/2] target/ppc/cpu-models: Rename power5+ and power7+ for " Thomas Huth
2024-01-17 15:22 ` Cédric Le Goater
2024-01-18 5:02 ` Harsh Prateek Bora [this message]
2024-01-17 14:10 ` [PATCH v2 2/2] docs/about: Deprecate the old "power5+" and "power7+" CPU names Thomas Huth
2024-01-17 15:19 ` Philippe Mathieu-Daudé
2024-01-17 15:22 ` Cédric Le Goater
2024-01-18 5:04 ` Harsh Prateek Bora
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=36491191-6b6c-4c7e-bfdd-ea58bcd38789@linux.ibm.com \
--to=harshpb@linux.ibm.com \
--cc=armbru@redhat.com \
--cc=clg@kaod.org \
--cc=danielhb413@gmail.com \
--cc=david@gibson.dropbear.id.au \
--cc=devel@lists.libvirt.org \
--cc=eduardo@habkost.net \
--cc=npiggin@gmail.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
--cc=thuth@redhat.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).