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Fri, 16 Apr 2021 15:38:20 +0000 (GMT) Received: from sig-9-145-157-105.de.ibm.com (unknown [9.145.157.105]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 16 Apr 2021 15:38:20 +0000 (GMT) Message-ID: <367a0f58dec6295474bd765b9cb2010e3e43e3cf.camel@linux.ibm.com> Subject: Re: [PATCH v4 2/4] target/arm: Make sure that commpage's tb->size != 0 From: Ilya Leoshkevich To: Peter Maydell Date: Fri, 16 Apr 2021 17:38:19 +0200 In-Reply-To: References: <20210415130305.28640-1-iii@linux.ibm.com> <20210415130305.28640-3-iii@linux.ibm.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.38.4 (3.38.4-1.fc33) MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: CcpTy7wTcHWYepGH6ADNZ2i8H7i1UVQ- X-Proofpoint-ORIG-GUID: FijzFKZiYCMv358IswAFoya2G544m_yX X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-04-16_08:2021-04-16, 2021-04-16 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=999 impostorscore=0 phishscore=0 mlxscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 malwarescore=0 clxscore=1015 bulkscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104060000 definitions=main-2104160112 Received-SPF: pass client-ip=148.163.156.1; envelope-from=iii@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , David Hildenbrand , Cornelia Huck , Richard Henderson , QEMU Developers , Max Filippov , qemu-s390x , qemu-arm , Paolo Bonzini , Christian Borntraeger Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, 2021-04-16 at 15:10 +0100, Peter Maydell wrote: > On Thu, 15 Apr 2021 at 14:03, Ilya Leoshkevich > wrote: > > > > tb_gen_code() assumes that tb->size must never be zero, otherwise > > it > > may produce spurious exceptions. For ARM this may happen when > > creating > > a translation block for the commpage. > > > > Fix by pretending that commpage translation blocks have at least > > one > > instruction. > > > > Signed-off-by: Ilya Leoshkevich > > --- > >  target/arm/translate.c | 1 + > >  1 file changed, 1 insertion(+) > > > > diff --git a/target/arm/translate.c b/target/arm/translate.c > > index 62b1c2081b..885f69b044 100644 > > --- a/target/arm/translate.c > > +++ b/target/arm/translate.c > > @@ -9060,6 +9060,7 @@ static void > > arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) > >      unsigned int insn; > > > >      if (arm_pre_translate_insn(dc)) { > > +        dc->base.pc_next += 4; > >          return; > >      } > > Why does the call to arm_pre_translate_insn() in > arm_tr_translate_insn() need > this change but not the one in thumb_tr_translate_insn() ? > > thanks > -- PMM > My bad: the regtest did not hit it, and I haven't thought about it. I will send a v5 with `dc->base.pc_next += 2;` there.