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From: "Heiko Stübner" <heiko@sntech.de>
To: Atish Patra <atishp@atishpatra.org>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Alistair Francis <alistair.francis@wdc.com>,
	Bin Meng <bin.meng@windriver.com>,
	Atish Patra <atishp@rivosinc.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH] target/riscv: Add isa extenstion strings to the device tree
Date: Tue, 15 Feb 2022 22:20:19 +0100	[thread overview]
Message-ID: <3681957.RLg0Pos3oq@diego> (raw)
In-Reply-To: <CAOnJCU+K6dKda0gwE_+V8qAp9CUg1RWseuCAOCPKoWs3_p6kUA@mail.gmail.com>

Am Dienstag, 15. Februar 2022, 20:39:10 CET schrieb Atish Patra:
> On Tue, Feb 15, 2022 at 8:20 AM Heiko Stübner <heiko@sntech.de> wrote:
> >
> > Am Dienstag, 15. Februar 2022, 10:05:30 CET schrieb Atish Patra:
> > > Append the available ISA extensions to the "riscv,isa" string if it
> > > is enabled so that kernel can process it.
> > >
> > > Signed-off-by: Atish Patra <atishp@rivosinc.com>
> > > ---
> > >  target/riscv/cpu.c | 23 ++++++++++++++++++++++-
> > >  1 file changed, 22 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > > index b0a40b83e7a8..c70260d0df15 100644
> > > --- a/target/riscv/cpu.c
> > > +++ b/target/riscv/cpu.c
> > > @@ -34,6 +34,9 @@
> > >
> > >  /* RISC-V CPU definitions */
> > >
> > > +/* This includes the null terminated character '\0' */
> > > +#define MAX_ISA_EXT_LEN 256
> > > +
> > >  static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
> > >
> > >  const char * const riscv_int_regnames[] = {
> > > @@ -881,10 +884,26 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
> > >      device_class_set_props(dc, riscv_cpu_properties);
> > >  }
> > >
> > > +static void riscv_isa_string_ext(RISCVCPU *cpu, char *isa_str, int max_str_len)
> > > +{
> > > +    int offset = strnlen(isa_str, max_str_len);
> > > +
> > > +    if (cpu->cfg.ext_svpbmt) {
> > > +        offset += snprintf(isa_str + offset, max_str_len, "_%s", "_svpbmt");
> > > +    }
> > > +    if ((offset < max_str_len) && cpu->cfg.ext_svinval) {
> >
> > shouldn't offset + strlen("svinval") +1 be < max_str_len?
> > snprintf will write partial strings but this would throw off a
> > qemu client completely I guess.
> >
> 
> We need that check to put out warnings to the user.

That is what I meant :-)

The current check above is for "there is still space for _something_"
but it doesn't check if the whole extension name fits.

That is what I'm trying to do in my example below check (and warn if not)
if the whole name fits into the remaining space.

> 
> >
> > > +        offset += snprintf(isa_str + offset, max_str_len, "_%s", "_svinval");
> > > +    }
> > > +    if ((offset < max_str_len) && (cpu->cfg.ext_svnapot)) {
> > > +        offset += snprintf(isa_str + offset, max_str_len, "_%s", "_svnapot");
> > > +    }
> >
> > wouldn't it make more sense to do something like:
> >
> > +    struct {
> > +        const char *value;
> > +        bool enabled;
> > +    } extensions[] = {
> > +        { "svpbmt", cpu->cfg.ext_svpbmt },
> > +        { "svinval", cpu->cfg.ext_svinval },
> > +        { "svnapot", cpu->cfg.ext_svnapot },
> > +    };
> > +    int i;
> > +
> > +    for (i = 0; i < ARRAY_SIZE(extensions); i++) {
> > +        if (!extensions[i].enabled)
> > +            continue;
> > +
> > +        /* check available space */
> > +        if (offset + strlen(extensions[i].value) + 1 > max_str_len) {
> > +            //do warn about exceeded length
> > +            return;
> > +        }
> > +
> > +        offset += snprintf(isa_str + offset, max_str_len, "_%s",
> > +                                                          extensions[i].value);
> > +    }
> >
> > instead?
> >
> > Because that list will get longer over time and repeating checks
> > and snprintf calls will get harder to keep in sync over time?
> >
> 
> Yeah. This is much better.
> 
> >
> > Heiko
> >
> >
> >
> >
> > > +}
> > > +
> > >  char *riscv_isa_string(RISCVCPU *cpu)
> > >  {
> > >      int i;
> > > -    const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
> > > +    const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) +
> > > +                          MAX_ISA_EXT_LEN;
> > >      char *isa_str = g_new(char, maxlen);
> > >      char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
> > >      for (i = 0; i < sizeof(riscv_exts); i++) {
> > > @@ -893,6 +912,8 @@ char *riscv_isa_string(RISCVCPU *cpu)
> > >          }
> > >      }
> > >      *p = '\0';
> > > +    riscv_isa_string_ext(cpu, isa_str, maxlen);
> > > +
> > >      return isa_str;
> > >  }
> > >
> > >
> >
> >
> >
> >
> >
> 
> 
> 






      reply	other threads:[~2022-02-15 21:22 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-15  9:05 [PATCH] target/riscv: Add isa extenstion strings to the device tree Atish Patra
2022-02-15  9:58 ` Heiko Stübner
2022-02-15 16:20 ` Heiko Stübner
2022-02-15 19:39   ` Atish Patra
2022-02-15 21:20     ` Heiko Stübner [this message]

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