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Tue, 22 Apr 2025 12:26:50 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ1PEPF00002320.mail.protection.outlook.com (10.167.242.86) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8655.12 via Frontend Transport; Tue, 22 Apr 2025 12:26:50 +0000 Received: from [10.136.47.77] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 22 Apr 2025 07:26:45 -0500 Message-ID: <36a69911-ff85-47e4-a34d-cf5e934d85da@amd.com> Date: Tue, 22 Apr 2025 17:56:37 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 08/18] amd_iommu: Helper to decode size of page invalidation command To: Alejandro Jimenez , CC: , , , , , , , , , , , , , , References: <20250414020253.443831-1-alejandro.j.jimenez@oracle.com> <20250414020253.443831-9-alejandro.j.jimenez@oracle.com> Content-Language: en-US From: Sairaj Kodilkar In-Reply-To: <20250414020253.443831-9-alejandro.j.jimenez@oracle.com> Content-Type: text/plain; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(376014)(7416014)(36860700013)(82310400026)(1800799024)(7053199007); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Apr 2025 12:26:50.3328 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 37755cad-b1d3-49ea-2020-08dd8198f52b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002320.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7429 Received-SPF: permerror client-ip=2a01:111:f403:2412::61e; envelope-from=Sairaj.ArunKodilkar@amd.com; helo=NAM10-MW2-obe.outbound.protection.outlook.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.411, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 4/14/2025 7:32 AM, Alejandro Jimenez wrote: > The size of the region to invalidate depends on the S bit and address > encoded in the command. Add a helper to extract this information, which > will be used to sync shadow page tables in upcoming changes. > > Signed-off-by: Alejandro Jimenez > --- > hw/i386/amd_iommu.c | 34 ++++++++++++++++++++++++++++++++++ > hw/i386/amd_iommu.h | 4 ++++ > 2 files changed, 38 insertions(+) > > diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c > index 5f55be1f4d36..0af873b66a31 100644 > --- a/hw/i386/amd_iommu.c > +++ b/hw/i386/amd_iommu.c > @@ -481,6 +481,40 @@ static gboolean amdvi_iotlb_remove_by_domid(gpointer key, gpointer value, > return entry->domid == domid; > } > > +/* > + * Helper to decode the size of the range to invalidate encoded in the > + * INVALIDATE_IOMMU_PAGES Command format. > + * The size of the region to invalidate depends on the S bit and address. > + * S bit value: > + * 0 : Invalidation size is 4 Kbytes. > + * 1 : Invalidation size is determined by first zero bit in the address > + * starting from Address[12]. > + * > + * In the AMD IOMMU Linux driver, an invalidation command with address > + * ((1 << 63) - 1) is sent when intending to clear the entire cache. > + * However, Table 14: Example Page Size Encodings shows that an address of > + * ((1ULL << 51) - 1) encodes the entire cache, so effectively any address with > + * first zero at bit 51 or larger is a request to invalidate the entire address > + * space. > + */ > +static uint64_t __attribute__((unused)) > +amdvi_decode_invalidation_size(hwaddr addr, uint16_t flags) > +{ > + uint64_t size = AMDVI_PAGE_SIZE; > + uint8_t fzbit = 0; > + > + if (flags & AMDVI_CMD_INVAL_IOMMU_PAGES_S) { > + fzbit = cto64(addr | 0xFFF); > + > + if (fzbit >= 51 || !addr) { I am skeptical about the condition addr == 0 (!addr) Consider the case where user wants to invalidate 8K size page, starting from address 0. It'll cause address field to be 0, right ? If so, then we should invalidate only 8K page not the entire address range. Am I missing something here ? Regards Sairaj > + size = AMDVI_INV_ALL_PAGES; > + } else {> + size = 1ULL << (fzbit + 1); > + } > + } > + return size; > +} > + > /* we don't have devid - we can't remove pages by address */ > static void amdvi_inval_pages(AMDVIState *s, uint64_t *cmd) > { > diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h > index e12ecade4baa..c89e7dc9947d 100644 > --- a/hw/i386/amd_iommu.h > +++ b/hw/i386/amd_iommu.h > @@ -123,6 +123,10 @@ > #define AMDVI_CMD_COMPLETE_PPR_REQUEST 0x07 > #define AMDVI_CMD_INVAL_AMDVI_ALL 0x08 > > + > +#define AMDVI_CMD_INVAL_IOMMU_PAGES_S (1ULL << 0) > +#define AMDVI_INV_ALL_PAGES (1ULL << 52) > + > #define AMDVI_DEVTAB_ENTRY_SIZE 32 > > /* Device table entry bits 0:63 */