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[176.184.11.147]) by smtp.gmail.com with ESMTPSA id dk18-20020a170907941200b00a58ca98bbfbsm762915ejc.30.2024.04.26.05.46.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 26 Apr 2024 05:46:52 -0700 (PDT) Message-ID: <36b9a714-44ff-4b60-a23d-89672a98f46e@linaro.org> Date: Fri, 26 Apr 2024 14:46:50 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/4] hw/watchdog/sbsa_gwdt: Make watchdog timer frequency a QOM property To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Radoslaw Biernacki , Leif Lindholm , Marcin Juszkiewicz References: <20240426122913.3427983-1-peter.maydell@linaro.org> <20240426122913.3427983-4-peter.maydell@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20240426122913.3427983-4-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=philmd@linaro.org; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Peter, On 26/4/24 14:29, Peter Maydell wrote: > Currently the sbsa_gdwt watchdog device hardcodes its frequency at > 62.5MHz. In real hardware, this watchdog is supposed to be driven > from the system counter, which also drives the CPU generic timers. > Newer CPU types (in particular from Armv8.6) should have a CPU > generic timer frequency of 1GHz, so we can't leave the watchdog > on the old QEMU default of 62.5GHz. > > Make the frequency a QOM property so it can be set by the board, > and have our only board that uses this device set that frequency > to the same value it sets the CPU frequency. > > Signed-off-by: Peter Maydell > --- > include/hw/watchdog/sbsa_gwdt.h | 3 +-- > hw/arm/sbsa-ref.c | 1 + > hw/watchdog/sbsa_gwdt.c | 15 ++++++++++++++- > 3 files changed, 16 insertions(+), 3 deletions(-) > diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c > index 36f6f717b4b..57c337fd92a 100644 > --- a/hw/arm/sbsa-ref.c > +++ b/hw/arm/sbsa-ref.c > @@ -543,6 +543,7 @@ static void create_wdt(const SBSAMachineState *sms) > SysBusDevice *s = SYS_BUS_DEVICE(dev); > int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0]; > > + qdev_prop_set_uint64(dev, "clock-frequency", SBSA_GTIMER_HZ); Since we have access to the CPU and its generic timer, what about just keep the wdg in sync, as smth like: qdev_prop_set_uint64(dev, "clock-frequency", object_property_get_uint(OBJECT(some_cpu), "cntfrq", errp)); > sysbus_realize_and_unref(s, &error_fatal); > sysbus_mmio_map(s, 0, rbase); > sysbus_mmio_map(s, 1, cbase);