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From: claude vittoria <vittoric@wanadoo.fr>
Message-ID: <3724340.369091197967780595.JavaMail.www@wwinf1b06>
Subject: Re: [Qemu-devel] [PPC] FPIMM macro and mtfsfi instruction
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Date: Tue, 18 Dec 2007 09:49:40 +0100 (CET)
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To: qemu-devel@nongnu.org

Hi Jocelyn,

Thanks for the quickly answer, but I got a wrong result again.

The actual version of mtfsfi translate.c:l2048 does not seem update the good flag.
The programmer environnement manual 32bits gives if Rc = 1 affected : copy of FX,FEX,VX,OX flags of FPSCR into CR1 of CR. Here, I only see the update of xer_so in CR.

Could you confirm my opinion ?

Regards,
Claude

/* mtfsfi */
GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
{
[...]
    if (unlikely(Rc(ctx->opcode) != 0)) {
        gen_op_load_fpcc();
        gen_op_set_Rc0();
    }
[...]
}

On Mon, 2007-12-17 at 15:52 +0100, claude vittoria wrote:
> Hi everybody,
> 
> I think that I get a wrong result with mtfsfi instruction.
> 
> I think to get a solution, see below.
> Could you confirm my opinion ?

Seems there have been (once again) a confusion between IBM bit notation
(0 is MSB...) and standard one. You're right, FPIMM should be taken
using EXTRACT_HELPER(FPIMM, 12, 4);

Thanks for the report.

> translate.c 
> l344:EXTRACT_HELPER(crbD, 21, 5);
> ...
> l375:EXTRACT_HELPER(FPIMM, 20, 4); <======FPIMM must be (FPIMM, 12, 4) or 
> crbB >> 1 for mtfsfi; IMM is bits[16-19] of the instruction in PPC 
> programming environnement 32bit (p8-135). IMM is not one bit before crbD.
> ...

[...]

-- 
Jocelyn Mayer <address@hidden>