Re: [Qemu-devel] [PPC] FPIMM macro and mtfsfi instruction

Re: [Qemu-devel] [PPC] FPIMM macro and mtfsfi instruction

[claude vittoria]

Hi Jocelyn,

Thanks for the quickly answer, but I got a wrong result again.

The actual version of mtfsfi translate.c:l2048 does not seem update the good flag.
The programmer environnement manual 32bits gives if Rc = 1 affected : copy of FX,FEX,VX,OX flags of FPSCR into CR1 of CR. Here, I only see the update of xer_so in CR.

Could you confirm my opinion ?

Regards,
Claude

/* mtfsfi */
GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
{
[...]
    if (unlikely(Rc(ctx->opcode) != 0)) {
        gen_op_load_fpcc();
        gen_op_set_Rc0();
    }
[...]
}

On Mon, 2007-12-17 at 15:52 +0100, claude vittoria wrote:
> Hi everybody,
> 
> I think that I get a wrong result with mtfsfi instruction.
> 
> I think to get a solution, see below.
> Could you confirm my opinion ?

Seems there have been (once again) a confusion between IBM bit notation
(0 is MSB...) and standard one. You're right, FPIMM should be taken
using EXTRACT_HELPER(FPIMM, 12, 4);

Thanks for the report.

> translate.c 
> l344:EXTRACT_HELPER(crbD, 21, 5);
> ...
> l375:EXTRACT_HELPER(FPIMM, 20, 4); <======FPIMM must be (FPIMM, 12, 4) or 
> crbB >> 1 for mtfsfi; IMM is bits[16-19] of the instruction in PPC 
> programming environnement 32bit (p8-135). IMM is not one bit before crbD.
> ...

[...]

-- 
Jocelyn Mayer <address@hidden>

[Qemu-devel] [PPC] FPIMM macro and mtfsfi instruction

[claude vittoria]

Hi everybody,

I think that I get a wrong result with mtfsfi instruction.

I think to get a solution, see below.
Could you confirm my opinion ?

Thanks,
Claude

translate.c 
l344:EXTRACT_HELPER(crbD, 21, 5);
...
l375:EXTRACT_HELPER(FPIMM, 20, 4); <======FPIMM must be (FPIMM, 12, 4) or crbB >> 1 for mtfsfi; IMM is bits[16-19] of the instruction in PPC programming environnement 32bit (p8-135). IMM is not one bit before crbD.
...
l2049
/* mtfsfi */
GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
{
    int bf, sh;

    if (unlikely(!ctx->fpu_enabled)) {
        GEN_EXCP_NO_FP(ctx);
        return;
    }
    bf = crbD(ctx->opcode) >> 2;                 <======================Ok bits[6-8]
    sh = 7 - bf;
    gen_optimize_fprf();
    gen_op_set_FT0(FPIMM(ctx->opcode) << (4 * sh)); <===================FPIMM is not correct, does not return the right value but bits [8-11]
    gen_reset_fpstatus();
    gen_op_store_fpscr(1 << sh);
    if (unlikely(Rc(ctx->opcode) != 0)) {
        gen_op_load_fpcc();
        gen_op_set_Rc0();
    }
    /* We can raise a differed exception */
    gen_op_float_check_status();
}

Re: [Qemu-devel] [PPC] FPIMM macro and mtfsfi instruction

[Jocelyn Mayer]

On Mon, 2007-12-17 at 15:52 +0100, claude vittoria wrote:
> Hi everybody,
> 
> I think that I get a wrong result with mtfsfi instruction.
> 
> I think to get a solution, see below.
> Could you confirm my opinion ?

Seems there have been (once again) a confusion between IBM bit notation
(0 is MSB...) and standard one. You're right, FPIMM should be taken
using EXTRACT_HELPER(FPIMM, 12, 4);

Thanks for the report.

> translate.c 
> l344:EXTRACT_HELPER(crbD, 21, 5);
> ...
> l375:EXTRACT_HELPER(FPIMM, 20, 4); <======FPIMM must be (FPIMM, 12, 4) or crbB >> 1 for mtfsfi; IMM is bits[16-19] of the instruction in PPC programming environnement 32bit (p8-135). IMM is not one bit before crbD.
> ...

[...]

-- 
Jocelyn Mayer <l_indien@magic.fr>