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([2602:ae:154e:e201:a7aa:1d1d:c857:5500]) by smtp.gmail.com with ESMTPSA id t17-20020a656091000000b00415d873b7a2sm1853743pgu.11.2022.08.12.16.27.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 12 Aug 2022 16:27:27 -0700 (PDT) Message-ID: <37244ef8-d2f1-038a-8a51-01d9f62fbe2c@linaro.org> Date: Fri, 12 Aug 2022 16:27:25 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH] riscv: Make semihosting configurable for all privilege modes Content-Language: en-US To: Furquan Shaikh , Palmer Dabbelt , Alistair Francis , Bin Meng , qemu-riscv@nongnu.org Cc: qemu-devel@nongnu.org References: From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 8/11/22 13:41, Furquan Shaikh wrote: > Unlike ARM, RISC-V does not define a separate breakpoint type for > semihosting. Instead, it is entirely ABI. Thus, we need an option > to allow users to configure what the ebreak behavior should be for > different privilege levels - M, S, U, VS, VU. As per the RISC-V > privilege specification[1], ebreak traps into the execution > environment. However, RISC-V debug specification[2] provides > ebreak{m,s,u,vs,vu} configuration bits to allow ebreak behavior to > be configured to trap into debug mode instead. This change adds > settable properties for RISC-V CPUs - `ebreakm`, `ebreaks`, `ebreaku`, > `ebreakvs` and `ebreakvu` to allow user to configure whether qemu > should treat ebreak as semihosting traps or trap according to the > privilege specification. > > [1] https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-privileged.pdf > [2] https://github.com/riscv/riscv-debug-spec/blob/release/riscv-debug-release.pdf I don't see why you need to change anything at all. Semihosting doesn't only use 'ebreak', but a sequence of 3 insns: slli x0, x0, 0x1f # 0x01f01013 Entry NOP ebreak # 0x00100073 Break to debugger srai x0, x0, 7 # 0x40705013 NOP encoding the semihosting call number 7 If the -semihosting command-line argument is absent, then the new DSCR fields apply as normal. If the -semihosting command-line argument is present, and the ebreak is not surrounded by the required nops, then the new DSCR fields apply as normal. But if the command-line argument is present and the nops are present, then semihosting overrides the architecture and DSCR does not apply at all. r~