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From: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <374e47e7-4d6d-0c77-0cbd-b2b665b41157@linaro.org>
Date: Thu, 22 Feb 2018 11:28:52 -0800
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Subject: Re: [Qemu-devel] [Qemu-arm] [PATCH v2 04/67] target/arm: Implement
 SVE Bitwise Logical - Unpredicated Group
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>, qemu-arm <qemu-arm@nongnu.org>

On 02/22/2018 10:04 AM, Peter Maydell wrote:
> On 17 February 2018 at 18:22, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>> These were the instructions that were stubbed out when
>> introducing the decode skeleton.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>>  target/arm/translate-sve.c | 50 +++++++++++++++++++++++++++++++++++++++-------
>>  1 file changed, 43 insertions(+), 7 deletions(-)
>>
>> diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
>> index 2c9e4733cb..50cf2a1fdd 100644
>> --- a/target/arm/translate-sve.c
>> +++ b/target/arm/translate-sve.c
>> @@ -32,6 +32,10 @@
>>  #include "trace-tcg.h"
>>  #include "translate-a64.h"
>>
>> +typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
>> +typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
>> +                        uint32_t, uint32_t, uint32_t);
> 
> I see we already have these in translate-a64.c -- put them in
> translate-a64.h ?

Good plan, thanks.


r~