[PATCH v2 00/23] target/loongarch: LoongArch32 fixes 1

[PATCH v2 00/23] target/loongarch: LoongArch32 fixes 1

[Jiaxun Yang]

Hi all,

It's boxing day so time to dump big stuff!

This series is a collection of small fixes I made to TCG for
getting LoongArch32 build to work.

There are still many thing broken, especially on CSRs. More
series following. A brief todo would be:
- Refactoring CSR handling to perform sign extention and handle RO
  fields.
- Refectoring TLB code to allow MTLB only configuration as well as
  special TLBELO format for LA32.
- Check instruction availability for LA32R.
- Handle LA32R priviliged modifications.

LoongArch maintainers, feel free to take subsets as most patches
in this series don't have dependency on each other, and I don't
want to take a pile of patches time by time.

There is a checkpatch error in trans_vec.c.inc inherited from
existing code style.

Thanks for revivewing!

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
Changes in v2:
- Dump all patches made ready so far.
- Split LLSC patch into two (Richard, philmd)
- Link to v1: https://lore.kernel.org/r/20241222-la32-fixes1-v1-0-8c62b7e594db@flygoat.com

---
Jiaxun Yang (23):
      target/loongarch: Enable rotr.w/rotri.w for LoongArch32
      target/loongarch: Fix address generation for gen_sc
      target/loongarch: Fix PGD CSR for LoongArch32
      target/loongarch: Perform sign extension for IOCSR reads
      target/loongarch: Use target_ulong for iocsrrd helper results
      target/loongarch: Store some uint64_t values as target_ulong
      target/loongarch: Cast address to 64bit before DMW_64_VSEG shift
      target/loongarch: Fix some modifiers for log formatting
      target/loongarch: Use target_ulong for CSR helpers
      target/loongarch: Scrutinise TCG float translation for 32 bit build
      target/loongarch: Scrutinise TCG vector translation for 32 bit build
      target/loongarch: Scrutinise TCG bitops translation for 32 bit build
      target/loongarch: Fix rdtimer on 32bit build
      target/loongarch: Scrutinise TCG arithmetic translation for 32 bit build
      target/loongarch: Fix load type for gen_ll
      target/loongarch: Define address space information for LoongArch32
      target/loongarch: Refactoring is_la64/is_va32 for LoongArch32
      target/loongarch: ifdef out 64 bit CPUs on 32 bit builds
      target/loongarch: Introduce max32 CPU type
      hw/loongarch/virt: Default to max32 CPU for LoongArch 32 build
      qapi/machine: Replace TARGET_LOONGARCH64 with TARGET_LOONGARCH
      target/loongarch: Wire up LoongArch32 Kconfigs
      config: Add loongarch32-softmmu target

 MAINTAINERS                                        |   4 +-
 configs/devices/loongarch32-softmmu/default.mak    |   7 +
 configs/targets/loongarch32-softmmu.mak            |   7 +
 hw/loongarch/Kconfig                               |   2 +-
 hw/loongarch/virt.c                                |   4 +
 qapi/machine-target.json                           |   8 +-
 target/loongarch/Kconfig                           |   3 +
 target/loongarch/cpu-param.h                       |  12 +-
 target/loongarch/cpu.c                             | 194 ++++++++++++++++-----
 target/loongarch/cpu.h                             | 150 ++++++++--------
 target/loongarch/cpu_helper.c                      |   2 +-
 target/loongarch/helper.h                          |  22 +--
 target/loongarch/machine.c                         | 120 ++++++-------
 target/loongarch/tcg/csr_helper.c                  |   2 +-
 target/loongarch/tcg/insn_trans/trans_arith.c.inc  |  25 ++-
 target/loongarch/tcg/insn_trans/trans_atomic.c.inc |   8 +-
 target/loongarch/tcg/insn_trans/trans_bit.c.inc    |  34 ++--
 target/loongarch/tcg/insn_trans/trans_extra.c.inc  |   8 +-
 target/loongarch/tcg/insn_trans/trans_farith.c.inc |  53 +++---
 target/loongarch/tcg/insn_trans/trans_fcmp.c.inc   |  16 +-
 .../loongarch/tcg/insn_trans/trans_fmemory.c.inc   |  34 ++--
 target/loongarch/tcg/insn_trans/trans_fmov.c.inc   |  83 ++++-----
 target/loongarch/tcg/insn_trans/trans_shift.c.inc  |   4 +-
 target/loongarch/tcg/insn_trans/trans_vec.c.inc    |  70 ++++----
 target/loongarch/tcg/iocsr_helper.c                |  20 +--
 target/loongarch/tcg/op_helper.c                   |   4 +-
 target/loongarch/tcg/tlb_helper.c                  |   2 +-
 target/loongarch/tcg/translate.c                   |  11 +-
 28 files changed, 537 insertions(+), 372 deletions(-)
---
base-commit: 65cb7129f4160c7e07a0da107f888ec73ae96776
change-id: 20241222-la32-fixes1-368cc14d0986

Best regards,
-- 
Jiaxun Yang <jiaxun.yang@flygoat.com>

[PATCH v2 01/23] target/loongarch: Enable rotr.w/rotri.w for LoongArch32

[Jiaxun Yang]

As per "LoongArch Reference Manual Volume 1: Basic Architecture" v1.1.0,
"2.2 Table 2. Application-level basic integer instructions in LA32",
rotr.w and rotri.w is a part of LA32 basic integer instructions.

Note that those instructions are indeed not in LA32R subset, however QEMU
is not performing any check against LA32R so far.

Make it available to ALL.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/tcg/insn_trans/trans_shift.c.inc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/loongarch/tcg/insn_trans/trans_shift.c.inc b/target/loongarch/tcg/insn_trans/trans_shift.c.inc
index 377307785aab4837bc181f1691632e7970a9889d..136c4c845527f0e63902a8306dcaf136dd4dd3fc 100644
--- a/target/loongarch/tcg/insn_trans/trans_shift.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_shift.c.inc
@@ -78,7 +78,7 @@ TRANS(sra_w, ALL, gen_rrr, EXT_SIGN, EXT_NONE, EXT_SIGN, gen_sra_w)
 TRANS(sll_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sll_d)
 TRANS(srl_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_srl_d)
 TRANS(sra_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sra_d)
-TRANS(rotr_w, 64, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_rotr_w)
+TRANS(rotr_w, ALL, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_rotr_w)
 TRANS(rotr_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rotr_d)
 TRANS(slli_w, ALL, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_shli_tl)
 TRANS(slli_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shli_tl)
@@ -86,5 +86,5 @@ TRANS(srli_w, ALL, gen_rri_c, EXT_ZERO, EXT_SIGN, tcg_gen_shri_tl)
 TRANS(srli_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shri_tl)
 TRANS(srai_w, ALL, gen_rri_c, EXT_NONE, EXT_NONE, gen_sari_w)
 TRANS(srai_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_sari_tl)
-TRANS(rotri_w, 64, gen_rri_v, EXT_NONE, EXT_NONE, gen_rotr_w)
+TRANS(rotri_w, ALL, gen_rri_v, EXT_NONE, EXT_NONE, gen_rotr_w)
 TRANS(rotri_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_rotri_tl)

-- 
2.43.0

[PATCH v2 02/23] target/loongarch: Fix address generation for gen_sc

[Jiaxun Yang]

gen_sc should use make_address_i to obtain source address
to ensure that address is properly truncated.

Another temp value is created in middle to avoid data corruption
as make_address_i may return the same memory location as src1.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
index 974bc2a70feddbf021a07b19a0859781eb3a11c4..c35f6f3ce47877ab6ad84fa2cbc50b46c0b23ad1 100644
--- a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
@@ -22,13 +22,12 @@ static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop)
     TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
     TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
     TCGv src2 = gpr_src(ctx, a->rd, EXT_NONE);
-    TCGv t0 = tcg_temp_new();
+    TCGv t0 = make_address_i(ctx, src1, a->imm);
     TCGv val = tcg_temp_new();
 
     TCGLabel *l1 = gen_new_label();
     TCGLabel *done = gen_new_label();
 
-    tcg_gen_addi_tl(t0, src1, a->imm);
     tcg_gen_brcond_tl(TCG_COND_EQ, t0, cpu_lladdr, l1);
     tcg_gen_movi_tl(dest, 0);
     tcg_gen_br(done);
@@ -36,6 +35,7 @@ static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop)
     gen_set_label(l1);
     tcg_gen_mov_tl(val, src2);
     /* generate cmpxchg */
+    t0 = tcg_temp_new();
     tcg_gen_atomic_cmpxchg_tl(t0, cpu_lladdr, cpu_llval,
                               val, ctx->mem_idx, mop);
     tcg_gen_setcond_tl(TCG_COND_EQ, dest, t0, cpu_llval);

-- 
2.43.0

[PATCH v2 03/23] target/loongarch: Fix PGD CSR for LoongArch32

[Jiaxun Yang]

As per manual, the source of PGD CSR is relevant to highest bit of
BADV. In LoongArch32, all CSRs are 32 bits only, thus we should check
bit 31 of BADV to determine PGDH/PGDL for LoongArch32.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/tcg/csr_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_helper.c
index 15f94caefabc7722263fa46e948e21de37b4203c..821aa6af46ea2129d771fdc937eca72317cefc1e 100644
--- a/target/loongarch/tcg/csr_helper.c
+++ b/target/loongarch/tcg/csr_helper.c
@@ -26,7 +26,7 @@ target_ulong helper_csrrd_pgd(CPULoongArchState *env)
         v = env->CSR_BADV;
     }
 
-    if ((v >> 63) & 0x1) {
+    if (extract64(v, is_la64(env) ? 63 : 31, 1)) {
         v = env->CSR_PGDH;
     } else {
         v = env->CSR_PGDL;

-- 
2.43.0

[PATCH v2 04/23] target/loongarch: Perform sign extension for IOCSR reads

[Jiaxun Yang]

As per LoongArch Reference Manual - Volume 1: Basic Architecture,
4.2.2. IOCSR Access Instructions:

The reading value is described as "writes it to the general register rd
after symbolic expansion." which means it should be sign extended.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/tcg/iocsr_helper.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/loongarch/tcg/iocsr_helper.c b/target/loongarch/tcg/iocsr_helper.c
index b6916f53d20ca133f0000e773685cb94240bafe2..db30de2523fff01bcc8923eb12c7fca7bedca7bf 100644
--- a/target/loongarch/tcg/iocsr_helper.c
+++ b/target/loongarch/tcg/iocsr_helper.c
@@ -17,20 +17,20 @@
 
 uint64_t helper_iocsrrd_b(CPULoongArchState *env, target_ulong r_addr)
 {
-    return address_space_ldub(env->address_space_iocsr, r_addr,
-                              GET_MEMTXATTRS(env), NULL);
+    return (int8_t)address_space_ldub(env->address_space_iocsr, r_addr,
+                                      GET_MEMTXATTRS(env), NULL);
 }
 
 uint64_t helper_iocsrrd_h(CPULoongArchState *env, target_ulong r_addr)
 {
-    return address_space_lduw(env->address_space_iocsr, r_addr,
-                              GET_MEMTXATTRS(env), NULL);
+    return (int16_t)address_space_lduw(env->address_space_iocsr, r_addr,
+                                       GET_MEMTXATTRS(env), NULL);
 }
 
 uint64_t helper_iocsrrd_w(CPULoongArchState *env, target_ulong r_addr)
 {
-    return address_space_ldl(env->address_space_iocsr, r_addr,
-                             GET_MEMTXATTRS(env), NULL);
+    return (int32_t)address_space_ldl(env->address_space_iocsr, r_addr,
+                                      GET_MEMTXATTRS(env), NULL);
 }
 
 uint64_t helper_iocsrrd_d(CPULoongArchState *env, target_ulong r_addr)

-- 
2.43.0

[PATCH v2 05/23] target/loongarch: Use target_ulong for iocsrrd helper results

[Jiaxun Yang]

Those results are all targeting TCGv values, which means they should
be in target_ulong type.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/helper.h           | 8 ++++----
 target/loongarch/tcg/iocsr_helper.c | 8 ++++----
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index b3b64a021536255a3f9decfc10ff61fe8380e2ae..409d93a5b0808f0e32b8c0e2e17cebac9feaf8ed 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -104,10 +104,10 @@ DEF_HELPER_2(csrwr_estat, i64, env, tl)
 DEF_HELPER_2(csrwr_asid, i64, env, tl)
 DEF_HELPER_2(csrwr_tcfg, i64, env, tl)
 DEF_HELPER_2(csrwr_ticlr, i64, env, tl)
-DEF_HELPER_2(iocsrrd_b, i64, env, tl)
-DEF_HELPER_2(iocsrrd_h, i64, env, tl)
-DEF_HELPER_2(iocsrrd_w, i64, env, tl)
-DEF_HELPER_2(iocsrrd_d, i64, env, tl)
+DEF_HELPER_2(iocsrrd_b, tl, env, tl)
+DEF_HELPER_2(iocsrrd_h, tl, env, tl)
+DEF_HELPER_2(iocsrrd_w, tl, env, tl)
+DEF_HELPER_2(iocsrrd_d, tl, env, tl)
 DEF_HELPER_3(iocsrwr_b, void, env, tl, tl)
 DEF_HELPER_3(iocsrwr_h, void, env, tl, tl)
 DEF_HELPER_3(iocsrwr_w, void, env, tl, tl)
diff --git a/target/loongarch/tcg/iocsr_helper.c b/target/loongarch/tcg/iocsr_helper.c
index db30de2523fff01bcc8923eb12c7fca7bedca7bf..23d819de0ef9790eb82741f1e8a0e20dc139bf4b 100644
--- a/target/loongarch/tcg/iocsr_helper.c
+++ b/target/loongarch/tcg/iocsr_helper.c
@@ -15,25 +15,25 @@
 #define GET_MEMTXATTRS(cas) \
         ((MemTxAttrs){.requester_id = env_cpu(cas)->cpu_index})
 
-uint64_t helper_iocsrrd_b(CPULoongArchState *env, target_ulong r_addr)
+target_ulong helper_iocsrrd_b(CPULoongArchState *env, target_ulong r_addr)
 {
     return (int8_t)address_space_ldub(env->address_space_iocsr, r_addr,
                                       GET_MEMTXATTRS(env), NULL);
 }
 
-uint64_t helper_iocsrrd_h(CPULoongArchState *env, target_ulong r_addr)
+target_ulong helper_iocsrrd_h(CPULoongArchState *env, target_ulong r_addr)
 {
     return (int16_t)address_space_lduw(env->address_space_iocsr, r_addr,
                                        GET_MEMTXATTRS(env), NULL);
 }
 
-uint64_t helper_iocsrrd_w(CPULoongArchState *env, target_ulong r_addr)
+target_ulong helper_iocsrrd_w(CPULoongArchState *env, target_ulong r_addr)
 {
     return (int32_t)address_space_ldl(env->address_space_iocsr, r_addr,
                                       GET_MEMTXATTRS(env), NULL);
 }
 
-uint64_t helper_iocsrrd_d(CPULoongArchState *env, target_ulong r_addr)
+target_ulong helper_iocsrrd_d(CPULoongArchState *env, target_ulong r_addr)
 {
     return address_space_ldq(env->address_space_iocsr, r_addr,
                              GET_MEMTXATTRS(env), NULL);

-- 
2.43.0

[PATCH v2 06/23] target/loongarch: Store some uint64_t values as target_ulong

[Jiaxun Yang]

Store internal registers including GPRs, CSRs, and LBT scratchs
as target_ulong, as per architecture specification.

The only exception here is tlb_misc, as it's only used by QEMU
internally and need keep to be 64bit to store all required fields.

There is no migration ABI change, as target_ulong is uint64_t on
existing loongarch64 builds anyway.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/cpu.c     |  34 ++++++------
 target/loongarch/cpu.h     | 132 ++++++++++++++++++++++-----------------------
 target/loongarch/machine.c | 120 ++++++++++++++++++++---------------------
 3 files changed, 143 insertions(+), 143 deletions(-)

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index f5bc8720d1fc1b28950ee02de5ae6cce86fc6a96..82412f8867a50a6cd25cff511def0f24d2b10b49 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -748,7 +748,7 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
     CPULoongArchState *env = cpu_env(cs);
     int i;
 
-    qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
+    qemu_fprintf(f, " PC=" TARGET_FMT_lx " ", env->pc);
     qemu_fprintf(f, " FCSR0 0x%08x\n", env->fcsr0);
 
     /* gpr */
@@ -756,28 +756,28 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
         if ((i & 3) == 0) {
             qemu_fprintf(f, " GPR%02d:", i);
         }
-        qemu_fprintf(f, " %s %016" PRIx64, regnames[i], env->gpr[i]);
+        qemu_fprintf(f, " %s " TARGET_FMT_lx, regnames[i], env->gpr[i]);
         if ((i & 3) == 3) {
             qemu_fprintf(f, "\n");
         }
     }
 
-    qemu_fprintf(f, "CRMD=%016" PRIx64 "\n", env->CSR_CRMD);
-    qemu_fprintf(f, "PRMD=%016" PRIx64 "\n", env->CSR_PRMD);
-    qemu_fprintf(f, "EUEN=%016" PRIx64 "\n", env->CSR_EUEN);
-    qemu_fprintf(f, "ESTAT=%016" PRIx64 "\n", env->CSR_ESTAT);
-    qemu_fprintf(f, "ERA=%016" PRIx64 "\n", env->CSR_ERA);
-    qemu_fprintf(f, "BADV=%016" PRIx64 "\n", env->CSR_BADV);
-    qemu_fprintf(f, "BADI=%016" PRIx64 "\n", env->CSR_BADI);
-    qemu_fprintf(f, "EENTRY=%016" PRIx64 "\n", env->CSR_EENTRY);
-    qemu_fprintf(f, "PRCFG1=%016" PRIx64 ", PRCFG2=%016" PRIx64 ","
-                 " PRCFG3=%016" PRIx64 "\n",
+    qemu_fprintf(f, "CRMD=" TARGET_FMT_lx "\n", env->CSR_CRMD);
+    qemu_fprintf(f, "PRMD=" TARGET_FMT_lx "\n", env->CSR_PRMD);
+    qemu_fprintf(f, "EUEN=" TARGET_FMT_lx "\n", env->CSR_EUEN);
+    qemu_fprintf(f, "ESTAT=" TARGET_FMT_lx "\n", env->CSR_ESTAT);
+    qemu_fprintf(f, "ERA=" TARGET_FMT_lx "\n", env->CSR_ERA);
+    qemu_fprintf(f, "BADV=" TARGET_FMT_lx "\n", env->CSR_BADV);
+    qemu_fprintf(f, "BADI=" TARGET_FMT_lx "\n", env->CSR_BADI);
+    qemu_fprintf(f, "EENTRY=" TARGET_FMT_lx "\n", env->CSR_EENTRY);
+    qemu_fprintf(f, "PRCFG1=" TARGET_FMT_lx ", PRCFG2=" TARGET_FMT_lx ","
+                 " PRCFG3=" TARGET_FMT_lx "\n",
                  env->CSR_PRCFG1, env->CSR_PRCFG2, env->CSR_PRCFG3);
-    qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY);
-    qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV);
-    qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA);
-    qemu_fprintf(f, "TCFG=%016" PRIx64 "\n", env->CSR_TCFG);
-    qemu_fprintf(f, "TVAL=%016" PRIx64 "\n", env->CSR_TVAL);
+    qemu_fprintf(f, "TLBRENTRY=" TARGET_FMT_lx "\n", env->CSR_TLBRENTRY);
+    qemu_fprintf(f, "TLBRBADV=" TARGET_FMT_lx "\n", env->CSR_TLBRBADV);
+    qemu_fprintf(f, "TLBRERA=" TARGET_FMT_lx "\n", env->CSR_TLBRERA);
+    qemu_fprintf(f, "TCFG=" TARGET_FMT_lx "\n", env->CSR_TCFG);
+    qemu_fprintf(f, "TVAL=" TARGET_FMT_lx "\n", env->CSR_TVAL);
 
     /* fpr */
     if (flags & CPU_DUMP_FPU) {
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 86c86c6c958db1a215a3e76a27f379bd4a095fb6..4f542a3376831141d012f177dc46a0e928afc85c 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -276,8 +276,8 @@ union fpr_t {
 struct LoongArchTLB {
     uint64_t tlb_misc;
     /* Fields corresponding to CSR_TLBELO0/1 */
-    uint64_t tlb_entry0;
-    uint64_t tlb_entry1;
+    target_ulong tlb_entry0;
+    target_ulong tlb_entry1;
 };
 typedef struct LoongArchTLB LoongArchTLB;
 #endif
@@ -289,18 +289,18 @@ enum loongarch_features {
 
 typedef struct  LoongArchBT {
     /* scratch registers */
-    uint64_t scr0;
-    uint64_t scr1;
-    uint64_t scr2;
-    uint64_t scr3;
+    target_ulong scr0;
+    target_ulong scr1;
+    target_ulong scr2;
+    target_ulong scr3;
     /* loongarch eflags */
     uint32_t eflags;
     uint32_t ftop;
 } lbt_t;
 
 typedef struct CPUArchState {
-    uint64_t gpr[32];
-    uint64_t pc;
+    target_ulong gpr[32];
+    target_ulong pc;
 
     fpr_t fpr[32];
     bool cf[8];
@@ -310,69 +310,69 @@ typedef struct CPUArchState {
     uint32_t cpucfg[21];
 
     /* LoongArch CSRs */
-    uint64_t CSR_CRMD;
-    uint64_t CSR_PRMD;
-    uint64_t CSR_EUEN;
-    uint64_t CSR_MISC;
-    uint64_t CSR_ECFG;
-    uint64_t CSR_ESTAT;
-    uint64_t CSR_ERA;
-    uint64_t CSR_BADV;
-    uint64_t CSR_BADI;
-    uint64_t CSR_EENTRY;
-    uint64_t CSR_TLBIDX;
-    uint64_t CSR_TLBEHI;
-    uint64_t CSR_TLBELO0;
-    uint64_t CSR_TLBELO1;
-    uint64_t CSR_ASID;
-    uint64_t CSR_PGDL;
-    uint64_t CSR_PGDH;
-    uint64_t CSR_PGD;
-    uint64_t CSR_PWCL;
-    uint64_t CSR_PWCH;
-    uint64_t CSR_STLBPS;
-    uint64_t CSR_RVACFG;
-    uint64_t CSR_CPUID;
-    uint64_t CSR_PRCFG1;
-    uint64_t CSR_PRCFG2;
-    uint64_t CSR_PRCFG3;
-    uint64_t CSR_SAVE[16];
-    uint64_t CSR_TID;
-    uint64_t CSR_TCFG;
-    uint64_t CSR_TVAL;
-    uint64_t CSR_CNTC;
-    uint64_t CSR_TICLR;
-    uint64_t CSR_LLBCTL;
-    uint64_t CSR_IMPCTL1;
-    uint64_t CSR_IMPCTL2;
-    uint64_t CSR_TLBRENTRY;
-    uint64_t CSR_TLBRBADV;
-    uint64_t CSR_TLBRERA;
-    uint64_t CSR_TLBRSAVE;
-    uint64_t CSR_TLBRELO0;
-    uint64_t CSR_TLBRELO1;
-    uint64_t CSR_TLBREHI;
-    uint64_t CSR_TLBRPRMD;
-    uint64_t CSR_MERRCTL;
-    uint64_t CSR_MERRINFO1;
-    uint64_t CSR_MERRINFO2;
-    uint64_t CSR_MERRENTRY;
-    uint64_t CSR_MERRERA;
-    uint64_t CSR_MERRSAVE;
-    uint64_t CSR_CTAG;
-    uint64_t CSR_DMW[4];
-    uint64_t CSR_DBG;
-    uint64_t CSR_DERA;
-    uint64_t CSR_DSAVE;
+    target_ulong CSR_CRMD;
+    target_ulong CSR_PRMD;
+    target_ulong CSR_EUEN;
+    target_ulong CSR_MISC;
+    target_ulong CSR_ECFG;
+    target_ulong CSR_ESTAT;
+    target_ulong CSR_ERA;
+    target_ulong CSR_BADV;
+    target_ulong CSR_BADI;
+    target_ulong CSR_EENTRY;
+    target_ulong CSR_TLBIDX;
+    target_ulong CSR_TLBEHI;
+    target_ulong CSR_TLBELO0;
+    target_ulong CSR_TLBELO1;
+    target_ulong CSR_ASID;
+    target_ulong CSR_PGDL;
+    target_ulong CSR_PGDH;
+    target_ulong CSR_PGD;
+    target_ulong CSR_PWCL;
+    target_ulong CSR_PWCH;
+    target_ulong CSR_STLBPS;
+    target_ulong CSR_RVACFG;
+    target_ulong CSR_CPUID;
+    target_ulong CSR_PRCFG1;
+    target_ulong CSR_PRCFG2;
+    target_ulong CSR_PRCFG3;
+    target_ulong CSR_SAVE[16];
+    target_ulong CSR_TID;
+    target_ulong CSR_TCFG;
+    target_ulong CSR_TVAL;
+    target_ulong CSR_CNTC;
+    target_ulong CSR_TICLR;
+    target_ulong CSR_LLBCTL;
+    target_ulong CSR_IMPCTL1;
+    target_ulong CSR_IMPCTL2;
+    target_ulong CSR_TLBRENTRY;
+    target_ulong CSR_TLBRBADV;
+    target_ulong CSR_TLBRERA;
+    target_ulong CSR_TLBRSAVE;
+    target_ulong CSR_TLBRELO0;
+    target_ulong CSR_TLBRELO1;
+    target_ulong CSR_TLBREHI;
+    target_ulong CSR_TLBRPRMD;
+    target_ulong CSR_MERRCTL;
+    target_ulong CSR_MERRINFO1;
+    target_ulong CSR_MERRINFO2;
+    target_ulong CSR_MERRENTRY;
+    target_ulong CSR_MERRERA;
+    target_ulong CSR_MERRSAVE;
+    target_ulong CSR_CTAG;
+    target_ulong CSR_DMW[4];
+    target_ulong CSR_DBG;
+    target_ulong CSR_DERA;
+    target_ulong CSR_DSAVE;
     struct {
-        uint64_t guest_addr;
+        target_ulong guest_addr;
     } stealtime;
 
 #ifdef CONFIG_TCG
     float_status fp_status;
     uint32_t fcsr0_mask;
-    uint64_t lladdr; /* LL virtual address compared against SC */
-    uint64_t llval;
+    target_ulong lladdr; /* LL virtual address compared against SC */
+    target_ulong llval;
 #endif
 #ifndef CONFIG_USER_ONLY
 #ifdef CONFIG_TCG
@@ -381,7 +381,7 @@ typedef struct CPUArchState {
 
     AddressSpace *address_space_iocsr;
     bool load_elf;
-    uint64_t elf_address;
+    target_ulong elf_address;
     uint32_t mp_state;
     /* Store ipistate to access from this struct */
     DeviceState *ipistate;
diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c
index 4e70f5c8798bdc826df809c98e8adb4ebf879c39..ba6e4f9df259c9a25962a4cfa180280f56ba6077 100644
--- a/target/loongarch/machine.c
+++ b/target/loongarch/machine.c
@@ -123,10 +123,10 @@ static const VMStateDescription vmstate_lbt = {
     .minimum_version_id = 0,
     .needed = lbt_needed,
     .fields = (const VMStateField[]) {
-        VMSTATE_UINT64(env.lbt.scr0,   LoongArchCPU),
-        VMSTATE_UINT64(env.lbt.scr1,   LoongArchCPU),
-        VMSTATE_UINT64(env.lbt.scr2,   LoongArchCPU),
-        VMSTATE_UINT64(env.lbt.scr3,   LoongArchCPU),
+        VMSTATE_UINTTL(env.lbt.scr0,   LoongArchCPU),
+        VMSTATE_UINTTL(env.lbt.scr1,   LoongArchCPU),
+        VMSTATE_UINTTL(env.lbt.scr2,   LoongArchCPU),
+        VMSTATE_UINTTL(env.lbt.scr3,   LoongArchCPU),
         VMSTATE_UINT32(env.lbt.eflags, LoongArchCPU),
         VMSTATE_UINT32(env.lbt.ftop,   LoongArchCPU),
         VMSTATE_END_OF_LIST()
@@ -146,8 +146,8 @@ static const VMStateDescription vmstate_tlb_entry = {
     .minimum_version_id = 0,
     .fields = (const VMStateField[]) {
         VMSTATE_UINT64(tlb_misc, LoongArchTLB),
-        VMSTATE_UINT64(tlb_entry0, LoongArchTLB),
-        VMSTATE_UINT64(tlb_entry1, LoongArchTLB),
+        VMSTATE_UINTTL(tlb_entry0, LoongArchTLB),
+        VMSTATE_UINTTL(tlb_entry1, LoongArchTLB),
         VMSTATE_END_OF_LIST()
     }
 };
@@ -175,65 +175,65 @@ const VMStateDescription vmstate_loongarch_cpu = {
         VMSTATE_UINTTL(env.pc, LoongArchCPU),
 
         /* Remaining CSRs */
-        VMSTATE_UINT64(env.CSR_CRMD, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_PRMD, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_EUEN, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_MISC, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_ECFG, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_ESTAT, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_ERA, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_BADV, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_BADI, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_EENTRY, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_TLBIDX, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_TLBEHI, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_TLBELO0, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_TLBELO1, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_ASID, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_PGDL, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_PGDH, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_PGD, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_PWCL, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_PWCH, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_STLBPS, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_RVACFG, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_PRCFG1, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_PRCFG2, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_PRCFG3, LoongArchCPU),
-        VMSTATE_UINT64_ARRAY(env.CSR_SAVE, LoongArchCPU, 16),
-        VMSTATE_UINT64(env.CSR_TID, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_TCFG, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_TVAL, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_CNTC, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_TICLR, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_LLBCTL, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_IMPCTL1, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_IMPCTL2, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_TLBRENTRY, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_TLBRBADV, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_TLBRERA, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_TLBRSAVE, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_TLBRELO0, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_TLBRELO1, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_TLBREHI, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_TLBRPRMD, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_MERRCTL, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_MERRINFO1, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_MERRINFO2, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_MERRENTRY, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_MERRERA, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_MERRSAVE, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_CTAG, LoongArchCPU),
-        VMSTATE_UINT64_ARRAY(env.CSR_DMW, LoongArchCPU, 4),
+        VMSTATE_UINTTL(env.CSR_CRMD, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_PRMD, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_EUEN, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_MISC, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_ECFG, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_ESTAT, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_ERA, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_BADV, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_BADI, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_EENTRY, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_TLBIDX, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_TLBEHI, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_TLBELO0, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_TLBELO1, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_ASID, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_PGDL, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_PGDH, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_PGD, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_PWCL, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_PWCH, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_STLBPS, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_RVACFG, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_PRCFG1, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_PRCFG2, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_PRCFG3, LoongArchCPU),
+        VMSTATE_UINTTL_ARRAY(env.CSR_SAVE, LoongArchCPU, 16),
+        VMSTATE_UINTTL(env.CSR_TID, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_TCFG, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_TVAL, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_CNTC, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_TICLR, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_LLBCTL, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_IMPCTL1, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_IMPCTL2, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_TLBRENTRY, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_TLBRBADV, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_TLBRERA, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_TLBRSAVE, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_TLBRELO0, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_TLBRELO1, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_TLBREHI, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_TLBRPRMD, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_MERRCTL, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_MERRINFO1, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_MERRINFO2, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_MERRENTRY, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_MERRERA, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_MERRSAVE, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_CTAG, LoongArchCPU),
+        VMSTATE_UINTTL_ARRAY(env.CSR_DMW, LoongArchCPU, 4),
 
         /* Debug CSRs */
-        VMSTATE_UINT64(env.CSR_DBG, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_DERA, LoongArchCPU),
-        VMSTATE_UINT64(env.CSR_DSAVE, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_DBG, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_DERA, LoongArchCPU),
+        VMSTATE_UINTTL(env.CSR_DSAVE, LoongArchCPU),
 
         VMSTATE_UINT64(kvm_state_counter, LoongArchCPU),
         /* PV steal time */
-        VMSTATE_UINT64(env.stealtime.guest_addr, LoongArchCPU),
+        VMSTATE_UINTTL(env.stealtime.guest_addr, LoongArchCPU),
 
         VMSTATE_END_OF_LIST()
     },

-- 
2.43.0

[PATCH v2 07/23] target/loongarch: Cast address to 64bit before DMW_64_VSEG shift

[Jiaxun Yang]

Avoid compiler warning on 32bit. This code path won't be taken anyway.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/cpu_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c
index 580362ac3e9ffbe6c8523cf57902dcda018ceed5..b8da136eb0554ba661a15e3069ee0d6bae61af86 100644
--- a/target/loongarch/cpu_helper.c
+++ b/target/loongarch/cpu_helper.c
@@ -196,7 +196,7 @@ int get_physical_address(CPULoongArchState *env, hwaddr *physical,
 
     plv = kernel_mode | (user_mode << R_CSR_DMW_PLV3_SHIFT);
     if (is_la64(env)) {
-        base_v = address >> R_CSR_DMW_64_VSEG_SHIFT;
+        base_v = (uint64_t)address >> R_CSR_DMW_64_VSEG_SHIFT;
     } else {
         base_v = address >> R_CSR_DMW_32_VSEG_SHIFT;
     }

-- 
2.43.0

[PATCH v2 08/23] target/loongarch: Fix some modifiers for log formatting

[Jiaxun Yang]

target_ulong -> TARGET_FMT_ld
vaddr -> VADDR_PRIx
uint32_t -> PRIx32

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
 target/loongarch/tcg/tlb_helper.c                  | 2 +-
 target/loongarch/tcg/translate.c                   | 5 ++---
 3 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
index c35f6f3ce47877ab6ad84fa2cbc50b46c0b23ad1..8584441b543712af8a56aa234c90fd6370c8df01 100644
--- a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
@@ -56,7 +56,7 @@ static bool gen_am(DisasContext *ctx, arg_rrr *a,
     if (a->rd != 0 && (a->rj == a->rd || a->rk == a->rd)) {
         qemu_log_mask(LOG_GUEST_ERROR,
                       "Warning: source register overlaps destination register"
-                      "in atomic insn at pc=0x" TARGET_FMT_lx "\n",
+                      "in atomic insn at pc=0x%016"VADDR_PRIx"\n",
                       ctx->base.pc_next - 4);
         return false;
     }
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 97f38fc391338ba4b76115b142fa76d89e45cd62..a1426b46f36c99e300ab924cb487875ec21ab226 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -517,7 +517,7 @@ target_ulong helper_lddir(CPULoongArchState *env, target_ulong base,
 
     if (unlikely((level == 0) || (level > 4))) {
         qemu_log_mask(LOG_GUEST_ERROR,
-                      "Attepted LDDIR with level %"PRId64"\n", level);
+                      "Attepted LDDIR with level "TARGET_FMT_ld"\n", level);
         return base;
     }
 
diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c
index 1fca4afc731c048816618d87610a0cc0fe7579b1..3939670e18d01bd9fc08861532166882fbd3f890 100644
--- a/target/loongarch/tcg/translate.c
+++ b/target/loongarch/tcg/translate.c
@@ -287,9 +287,8 @@ static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
     ctx->opcode = translator_ldl(cpu_env(cs), &ctx->base, ctx->base.pc_next);
 
     if (!decode(ctx, ctx->opcode)) {
-        qemu_log_mask(LOG_UNIMP, "Error: unknown opcode. "
-                      TARGET_FMT_lx ": 0x%x\n",
-                      ctx->base.pc_next, ctx->opcode);
+        qemu_log_mask(LOG_UNIMP, "Error: unknown opcode. %016"VADDR_PRIx
+                      ": 0x%08"PRIx32"\n", ctx->base.pc_next, ctx->opcode);
         generate_exception(ctx, EXCCODE_INE);
     }
 

-- 
2.43.0

[PATCH v2 09/23] target/loongarch: Use target_ulong for CSR helpers

[Jiaxun Yang]

All CSRs are meant to be target_ulong wide in our setting.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/helper.h        | 14 +++++++-------
 target/loongarch/tcg/op_helper.c |  4 ++--
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 409d93a5b0808f0e32b8c0e2e17cebac9feaf8ed..a608754b7f52689da9e9f4da1cef68d5af72f2ed 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -97,13 +97,13 @@ DEF_HELPER_1(rdtime_d, i64, env)
 
 #ifndef CONFIG_USER_ONLY
 /* CSRs helper */
-DEF_HELPER_1(csrrd_pgd, i64, env)
-DEF_HELPER_1(csrrd_cpuid, i64, env)
-DEF_HELPER_1(csrrd_tval, i64, env)
-DEF_HELPER_2(csrwr_estat, i64, env, tl)
-DEF_HELPER_2(csrwr_asid, i64, env, tl)
-DEF_HELPER_2(csrwr_tcfg, i64, env, tl)
-DEF_HELPER_2(csrwr_ticlr, i64, env, tl)
+DEF_HELPER_1(csrrd_pgd, tl, env)
+DEF_HELPER_1(csrrd_cpuid, tl, env)
+DEF_HELPER_1(csrrd_tval, tl, env)
+DEF_HELPER_2(csrwr_estat, tl, env, tl)
+DEF_HELPER_2(csrwr_asid, tl, env, tl)
+DEF_HELPER_2(csrwr_tcfg, tl, env, tl)
+DEF_HELPER_2(csrwr_ticlr, tl, env, tl)
 DEF_HELPER_2(iocsrrd_b, tl, env, tl)
 DEF_HELPER_2(iocsrrd_h, tl, env, tl)
 DEF_HELPER_2(iocsrrd_w, tl, env, tl)
diff --git a/target/loongarch/tcg/op_helper.c b/target/loongarch/tcg/op_helper.c
index b17208e5b962f2191b2afa60181bff311d618bba..c9d7e84e7ec9000bab655366bdf6ed8aaa4fd080 100644
--- a/target/loongarch/tcg/op_helper.c
+++ b/target/loongarch/tcg/op_helper.c
@@ -61,7 +61,7 @@ void helper_asrtgt_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
     }
 }
 
-target_ulong helper_crc32(target_ulong val, target_ulong m, uint64_t sz)
+target_ulong helper_crc32(target_ulong val, target_ulong m, target_ulong sz)
 {
     uint8_t buf[8];
     target_ulong mask = ((sz * 8) == 64) ? -1ULL : ((1ULL << (sz * 8)) - 1);
@@ -71,7 +71,7 @@ target_ulong helper_crc32(target_ulong val, target_ulong m, uint64_t sz)
     return (int32_t) (crc32(val ^ 0xffffffff, buf, sz) ^ 0xffffffff);
 }
 
-target_ulong helper_crc32c(target_ulong val, target_ulong m, uint64_t sz)
+target_ulong helper_crc32c(target_ulong val, target_ulong m, target_ulong sz)
 {
     uint8_t buf[8];
     target_ulong mask = ((sz * 8) == 64) ? -1ULL : ((1ULL << (sz * 8)) - 1);

-- 
2.43.0

[PATCH v2 10/23] target/loongarch: Scrutinise TCG float translation for 32 bit build

[Jiaxun Yang]

All float computations are kept to be 64 bit, fix types for various TCGv.

Performing TCGv type conversion as necessary when interaction with GPR
happens.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/tcg/insn_trans/trans_farith.c.inc | 53 +++++++-------
 target/loongarch/tcg/insn_trans/trans_fcmp.c.inc   | 16 ++---
 .../loongarch/tcg/insn_trans/trans_fmemory.c.inc   | 34 ++++-----
 target/loongarch/tcg/insn_trans/trans_fmov.c.inc   | 83 ++++++++++++----------
 target/loongarch/tcg/translate.c                   |  6 +-
 5 files changed, 99 insertions(+), 93 deletions(-)

diff --git a/target/loongarch/tcg/insn_trans/trans_farith.c.inc b/target/loongarch/tcg/insn_trans/trans_farith.c.inc
index f4a0dea72701a99954d8ff8fc9be2eb55e2f39a8..de8101334c67285dba801309bcd652f54326ad25 100644
--- a/target/loongarch/tcg/insn_trans/trans_farith.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_farith.c.inc
@@ -15,11 +15,11 @@
 #endif
 
 static bool gen_fff(DisasContext *ctx, arg_fff *a,
-                    void (*func)(TCGv, TCGv_env, TCGv, TCGv))
+                    void (*func)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64))
 {
-    TCGv dest = get_fpr(ctx, a->fd);
-    TCGv src1 = get_fpr(ctx, a->fj);
-    TCGv src2 = get_fpr(ctx, a->fk);
+    TCGv_i64 dest = get_fpr(ctx, a->fd);
+    TCGv_i64 src1 = get_fpr(ctx, a->fj);
+    TCGv_i64 src2 = get_fpr(ctx, a->fk);
 
     CHECK_FPE;
 
@@ -30,10 +30,10 @@ static bool gen_fff(DisasContext *ctx, arg_fff *a,
 }
 
 static bool gen_ff(DisasContext *ctx, arg_ff *a,
-                   void (*func)(TCGv, TCGv_env, TCGv))
+                   void (*func)(TCGv_i64, TCGv_env, TCGv_i64))
 {
-    TCGv dest = get_fpr(ctx, a->fd);
-    TCGv src = get_fpr(ctx, a->fj);
+    TCGv_i64 dest = get_fpr(ctx, a->fd);
+    TCGv_i64 src = get_fpr(ctx, a->fj);
 
     CHECK_FPE;
 
@@ -44,14 +44,15 @@ static bool gen_ff(DisasContext *ctx, arg_ff *a,
 }
 
 static bool gen_muladd(DisasContext *ctx, arg_ffff *a,
-                       void (*func)(TCGv, TCGv_env, TCGv, TCGv, TCGv, TCGv_i32),
+                       void (*func)(TCGv_i64, TCGv_env, TCGv_i64,
+                                    TCGv_i64, TCGv_i64, TCGv_i32),
                        int flag)
 {
     TCGv_i32 tflag = tcg_constant_i32(flag);
-    TCGv dest = get_fpr(ctx, a->fd);
-    TCGv src1 = get_fpr(ctx, a->fj);
-    TCGv src2 = get_fpr(ctx, a->fk);
-    TCGv src3 = get_fpr(ctx, a->fa);
+    TCGv_i64 dest = get_fpr(ctx, a->fd);
+    TCGv_i64 src1 = get_fpr(ctx, a->fj);
+    TCGv_i64 src2 = get_fpr(ctx, a->fk);
+    TCGv_i64 src3 = get_fpr(ctx, a->fa);
 
     CHECK_FPE;
 
@@ -63,9 +64,9 @@ static bool gen_muladd(DisasContext *ctx, arg_ffff *a,
 
 static bool trans_fcopysign_s(DisasContext *ctx, arg_fcopysign_s *a)
 {
-    TCGv dest = get_fpr(ctx, a->fd);
-    TCGv src1 = get_fpr(ctx, a->fk);
-    TCGv src2 = get_fpr(ctx, a->fj);
+    TCGv_i64 dest = get_fpr(ctx, a->fd);
+    TCGv_i64 src1 = get_fpr(ctx, a->fk);
+    TCGv_i64 src2 = get_fpr(ctx, a->fj);
 
     if (!avail_FP_SP(ctx)) {
         return false;
@@ -81,9 +82,9 @@ static bool trans_fcopysign_s(DisasContext *ctx, arg_fcopysign_s *a)
 
 static bool trans_fcopysign_d(DisasContext *ctx, arg_fcopysign_d *a)
 {
-    TCGv dest = get_fpr(ctx, a->fd);
-    TCGv src1 = get_fpr(ctx, a->fk);
-    TCGv src2 = get_fpr(ctx, a->fj);
+    TCGv_i64 dest = get_fpr(ctx, a->fd);
+    TCGv_i64 src1 = get_fpr(ctx, a->fk);
+    TCGv_i64 src2 = get_fpr(ctx, a->fj);
 
     if (!avail_FP_DP(ctx)) {
         return false;
@@ -99,8 +100,8 @@ static bool trans_fcopysign_d(DisasContext *ctx, arg_fcopysign_d *a)
 
 static bool trans_fabs_s(DisasContext *ctx, arg_fabs_s *a)
 {
-    TCGv dest = get_fpr(ctx, a->fd);
-    TCGv src = get_fpr(ctx, a->fj);
+    TCGv_i64 dest = get_fpr(ctx, a->fd);
+    TCGv_i64 src = get_fpr(ctx, a->fj);
 
     if (!avail_FP_SP(ctx)) {
         return false;
@@ -117,8 +118,8 @@ static bool trans_fabs_s(DisasContext *ctx, arg_fabs_s *a)
 
 static bool trans_fabs_d(DisasContext *ctx, arg_fabs_d *a)
 {
-    TCGv dest = get_fpr(ctx, a->fd);
-    TCGv src = get_fpr(ctx, a->fj);
+    TCGv_i64 dest = get_fpr(ctx, a->fd);
+    TCGv_i64 src = get_fpr(ctx, a->fj);
 
     if (!avail_FP_DP(ctx)) {
         return false;
@@ -134,8 +135,8 @@ static bool trans_fabs_d(DisasContext *ctx, arg_fabs_d *a)
 
 static bool trans_fneg_s(DisasContext *ctx, arg_fneg_s *a)
 {
-    TCGv dest = get_fpr(ctx, a->fd);
-    TCGv src = get_fpr(ctx, a->fj);
+    TCGv_i64 dest = get_fpr(ctx, a->fd);
+    TCGv_i64 src = get_fpr(ctx, a->fj);
 
     if (!avail_FP_SP(ctx)) {
         return false;
@@ -152,8 +153,8 @@ static bool trans_fneg_s(DisasContext *ctx, arg_fneg_s *a)
 
 static bool trans_fneg_d(DisasContext *ctx, arg_fneg_d *a)
 {
-    TCGv dest = get_fpr(ctx, a->fd);
-    TCGv src = get_fpr(ctx, a->fj);
+    TCGv_i64 dest = get_fpr(ctx, a->fd);
+    TCGv_i64 src = get_fpr(ctx, a->fj);
 
     if (!avail_FP_DP(ctx)) {
         return false;
diff --git a/target/loongarch/tcg/insn_trans/trans_fcmp.c.inc b/target/loongarch/tcg/insn_trans/trans_fcmp.c.inc
index 3babf69e4ab556842be2a83a98215da607d9a044..f0cefc75070825469bac09c59d11637d35586602 100644
--- a/target/loongarch/tcg/insn_trans/trans_fcmp.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_fcmp.c.inc
@@ -25,9 +25,9 @@ static uint32_t get_fcmp_flags(int cond)
 
 static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fcmp_cond_s *a)
 {
-    TCGv var, src1, src2;
+    TCGv_i64 var, src1, src2;
     uint32_t flags;
-    void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32);
+    void (*fn)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64, TCGv_i32);
 
     if (!avail_FP_SP(ctx)) {
         return false;
@@ -35,7 +35,7 @@ static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fcmp_cond_s *a)
 
     CHECK_FPE;
 
-    var = tcg_temp_new();
+    var = tcg_temp_new_i64();
     src1 = get_fpr(ctx, a->fj);
     src2 = get_fpr(ctx, a->fk);
     fn = (a->fcond & 1 ? gen_helper_fcmp_s_s : gen_helper_fcmp_c_s);
@@ -43,15 +43,15 @@ static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fcmp_cond_s *a)
 
     fn(var, tcg_env, src1, src2, tcg_constant_i32(flags));
 
-    tcg_gen_st8_tl(var, tcg_env, offsetof(CPULoongArchState, cf[a->cd]));
+    tcg_gen_st8_i64(var, tcg_env, offsetof(CPULoongArchState, cf[a->cd]));
     return true;
 }
 
 static bool trans_fcmp_cond_d(DisasContext *ctx, arg_fcmp_cond_d *a)
 {
-    TCGv var, src1, src2;
+    TCGv_i64 var, src1, src2;
     uint32_t flags;
-    void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32);
+    void (*fn)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64, TCGv_i32);
 
     if (!avail_FP_DP(ctx)) {
         return false;
@@ -59,7 +59,7 @@ static bool trans_fcmp_cond_d(DisasContext *ctx, arg_fcmp_cond_d *a)
 
     CHECK_FPE;
 
-    var = tcg_temp_new();
+    var = tcg_temp_new_i64();
     src1 = get_fpr(ctx, a->fj);
     src2 = get_fpr(ctx, a->fk);
     fn = (a->fcond & 1 ? gen_helper_fcmp_s_d : gen_helper_fcmp_c_d);
@@ -67,6 +67,6 @@ static bool trans_fcmp_cond_d(DisasContext *ctx, arg_fcmp_cond_d *a)
 
     fn(var, tcg_env, src1, src2, tcg_constant_i32(flags));
 
-    tcg_gen_st8_tl(var, tcg_env, offsetof(CPULoongArchState, cf[a->cd]));
+    tcg_gen_st8_i64(var, tcg_env, offsetof(CPULoongArchState, cf[a->cd]));
     return true;
 }
diff --git a/target/loongarch/tcg/insn_trans/trans_fmemory.c.inc b/target/loongarch/tcg/insn_trans/trans_fmemory.c.inc
index 13452bc7e56aef1ae7388d37bc45776cba536a75..79e2506157ab04e68cf8d7091038ecce75a4683a 100644
--- a/target/loongarch/tcg/insn_trans/trans_fmemory.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_fmemory.c.inc
@@ -3,7 +3,7 @@
  * Copyright (c) 2021 Loongson Technology Corporation Limited
  */
 
-static void maybe_nanbox_load(TCGv freg, MemOp mop)
+static void maybe_nanbox_load(TCGv_i64 freg, MemOp mop)
 {
     if ((mop & MO_SIZE) == MO_32) {
         gen_nanbox_s(freg, freg);
@@ -13,13 +13,13 @@ static void maybe_nanbox_load(TCGv freg, MemOp mop)
 static bool gen_fload_i(DisasContext *ctx, arg_fr_i *a, MemOp mop)
 {
     TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
-    TCGv dest = get_fpr(ctx, a->fd);
+    TCGv_i64 dest = get_fpr(ctx, a->fd);
 
     CHECK_FPE;
 
     addr = make_address_i(ctx, addr, a->imm);
 
-    tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
+    tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, mop);
     maybe_nanbox_load(dest, mop);
     set_fpr(a->fd, dest);
 
@@ -29,13 +29,13 @@ static bool gen_fload_i(DisasContext *ctx, arg_fr_i *a, MemOp mop)
 static bool gen_fstore_i(DisasContext *ctx, arg_fr_i *a, MemOp mop)
 {
     TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
-    TCGv src = get_fpr(ctx, a->fd);
+    TCGv_i64 src = get_fpr(ctx, a->fd);
 
     CHECK_FPE;
 
     addr = make_address_i(ctx, addr, a->imm);
 
-    tcg_gen_qemu_st_tl(src, addr, ctx->mem_idx, mop);
+    tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, mop);
 
     return true;
 }
@@ -44,13 +44,13 @@ static bool gen_floadx(DisasContext *ctx, arg_frr *a, MemOp mop)
 {
     TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
     TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
-    TCGv dest = get_fpr(ctx, a->fd);
+    TCGv_i64 dest = get_fpr(ctx, a->fd);
     TCGv addr;
 
     CHECK_FPE;
 
     addr = make_address_x(ctx, src1, src2);
-    tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
+    tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, mop);
     maybe_nanbox_load(dest, mop);
     set_fpr(a->fd, dest);
 
@@ -61,13 +61,13 @@ static bool gen_fstorex(DisasContext *ctx, arg_frr *a, MemOp mop)
 {
     TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
     TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
-    TCGv src3 = get_fpr(ctx, a->fd);
+    TCGv_i64 src3 = get_fpr(ctx, a->fd);
     TCGv addr;
 
     CHECK_FPE;
 
     addr = make_address_x(ctx, src1, src2);
-    tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop);
+    tcg_gen_qemu_st_i64(src3, addr, ctx->mem_idx, mop);
 
     return true;
 }
@@ -76,14 +76,14 @@ static bool gen_fload_gt(DisasContext *ctx, arg_frr *a, MemOp mop)
 {
     TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
     TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
-    TCGv dest = get_fpr(ctx, a->fd);
+    TCGv_i64 dest = get_fpr(ctx, a->fd);
     TCGv addr;
 
     CHECK_FPE;
 
     gen_helper_asrtgt_d(tcg_env, src1, src2);
     addr = make_address_x(ctx, src1, src2);
-    tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
+    tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, mop);
     maybe_nanbox_load(dest, mop);
     set_fpr(a->fd, dest);
 
@@ -94,14 +94,14 @@ static bool gen_fstore_gt(DisasContext *ctx, arg_frr *a, MemOp mop)
 {
     TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
     TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
-    TCGv src3 = get_fpr(ctx, a->fd);
+    TCGv_i64 src3 = get_fpr(ctx, a->fd);
     TCGv addr;
 
     CHECK_FPE;
 
     gen_helper_asrtgt_d(tcg_env, src1, src2);
     addr = make_address_x(ctx, src1, src2);
-    tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop);
+    tcg_gen_qemu_st_i64(src3, addr, ctx->mem_idx, mop);
 
     return true;
 }
@@ -110,14 +110,14 @@ static bool gen_fload_le(DisasContext *ctx, arg_frr *a, MemOp mop)
 {
     TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
     TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
-    TCGv dest = get_fpr(ctx, a->fd);
+    TCGv_i64 dest = get_fpr(ctx, a->fd);
     TCGv addr;
 
     CHECK_FPE;
 
     gen_helper_asrtle_d(tcg_env, src1, src2);
     addr = make_address_x(ctx, src1, src2);
-    tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
+    tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, mop);
     maybe_nanbox_load(dest, mop);
     set_fpr(a->fd, dest);
 
@@ -128,14 +128,14 @@ static bool gen_fstore_le(DisasContext *ctx, arg_frr *a, MemOp mop)
 {
     TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
     TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
-    TCGv src3 = get_fpr(ctx, a->fd);
+    TCGv_i64 src3 = get_fpr(ctx, a->fd);
     TCGv addr;
 
     CHECK_FPE;
 
     gen_helper_asrtle_d(tcg_env, src1, src2);
     addr = make_address_x(ctx, src1, src2);
-    tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop);
+    tcg_gen_qemu_st_i64(src3, addr, ctx->mem_idx, mop);
 
     return true;
 }
diff --git a/target/loongarch/tcg/insn_trans/trans_fmov.c.inc b/target/loongarch/tcg/insn_trans/trans_fmov.c.inc
index 5cbd9d3f347128852ba1933a5961148464f1bbf5..58ce4d3c45d84a5de19358dd289b87aef2cb1078 100644
--- a/target/loongarch/tcg/insn_trans/trans_fmov.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_fmov.c.inc
@@ -9,11 +9,11 @@ static const uint32_t fcsr_mask[4] = {
 
 static bool trans_fsel(DisasContext *ctx, arg_fsel *a)
 {
-    TCGv zero = tcg_constant_tl(0);
-    TCGv dest = get_fpr(ctx, a->fd);
-    TCGv src1 = get_fpr(ctx, a->fj);
-    TCGv src2 = get_fpr(ctx, a->fk);
-    TCGv cond;
+    TCGv_i64 zero = tcg_constant_i64(0);
+    TCGv_i64 dest = get_fpr(ctx, a->fd);
+    TCGv_i64 src1 = get_fpr(ctx, a->fj);
+    TCGv_i64 src2 = get_fpr(ctx, a->fk);
+    TCGv_i64 cond;
 
     if (!avail_FP(ctx)) {
         return false;
@@ -21,19 +21,19 @@ static bool trans_fsel(DisasContext *ctx, arg_fsel *a)
 
     CHECK_FPE;
 
-    cond = tcg_temp_new();
-    tcg_gen_ld8u_tl(cond, tcg_env, offsetof(CPULoongArchState, cf[a->ca]));
-    tcg_gen_movcond_tl(TCG_COND_EQ, dest, cond, zero, src1, src2);
+    cond = tcg_temp_new_i64();
+    tcg_gen_ld8u_i64(cond, tcg_env, offsetof(CPULoongArchState, cf[a->ca]));
+    tcg_gen_movcond_i64(TCG_COND_EQ, dest, cond, zero, src1, src2);
     set_fpr(a->fd, dest);
 
     return true;
 }
 
 static bool gen_f2f(DisasContext *ctx, arg_ff *a,
-                    void (*func)(TCGv, TCGv), bool nanbox)
+                    void (*func)(TCGv_i64, TCGv_i64), bool nanbox)
 {
-    TCGv dest = get_fpr(ctx, a->fd);
-    TCGv src = get_fpr(ctx, a->fj);
+    TCGv_i64 dest = get_fpr(ctx, a->fd);
+    TCGv_i64 src = get_fpr(ctx, a->fj);
 
     CHECK_FPE;
 
@@ -47,17 +47,18 @@ static bool gen_f2f(DisasContext *ctx, arg_ff *a,
 }
 
 static bool gen_r2f(DisasContext *ctx, arg_fr *a,
-                    void (*func)(TCGv, TCGv))
+                    void (*func)(TCGv_i64, TCGv_i64))
 {
-    TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
-    TCGv dest = get_fpr(ctx, a->fd);
+    TCGv rj = gpr_src(ctx, a->rj, EXT_NONE);
+    TCGv_i64 dest = get_fpr(ctx, a->fd);
+    TCGv_i64 src = tcg_temp_new_i64();
 
     if (!avail_FP(ctx)) {
         return false;
     }
 
     CHECK_FPE;
-
+    tcg_gen_ext_tl_i64(src, rj);
     func(dest, src);
     set_fpr(a->fd, dest);
 
@@ -65,10 +66,11 @@ static bool gen_r2f(DisasContext *ctx, arg_fr *a,
 }
 
 static bool gen_f2r(DisasContext *ctx, arg_rf *a,
-                    void (*func)(TCGv, TCGv))
+                    void (*func)(TCGv_i64, TCGv_i64))
 {
-    TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
-    TCGv src = get_fpr(ctx, a->fj);
+    TCGv rd = gpr_dst(ctx, a->rd, EXT_NONE);
+    TCGv_i64 src = get_fpr(ctx, a->fj);
+    TCGv_i64 dest = tcg_temp_new_i64();
 
     if (!avail_FP(ctx)) {
         return false;
@@ -77,7 +79,8 @@ static bool gen_f2r(DisasContext *ctx, arg_rf *a,
     CHECK_FPE;
 
     func(dest, src);
-    gen_set_gpr(a->rd, dest, EXT_NONE);
+    tcg_gen_trunc_i64_tl(rd, dest);
+    gen_set_gpr(a->rd, rd, EXT_NONE);
 
     return true;
 }
@@ -94,13 +97,13 @@ static bool trans_movgr2fcsr(DisasContext *ctx, arg_movgr2fcsr *a)
     CHECK_FPE;
 
     if (mask == UINT32_MAX) {
-        tcg_gen_st32_i64(Rj, tcg_env, offsetof(CPULoongArchState, fcsr0));
+        tcg_gen_st32_tl(Rj, tcg_env, offsetof(CPULoongArchState, fcsr0));
     } else {
         TCGv_i32 fcsr0 = tcg_temp_new_i32();
         TCGv_i32 temp = tcg_temp_new_i32();
 
         tcg_gen_ld_i32(fcsr0, tcg_env, offsetof(CPULoongArchState, fcsr0));
-        tcg_gen_extrl_i64_i32(temp, Rj);
+        tcg_gen_trunc_tl_i32(temp, Rj);
         tcg_gen_andi_i32(temp, temp, mask);
         tcg_gen_andi_i32(fcsr0, fcsr0, ~mask);
         tcg_gen_or_i32(fcsr0, fcsr0, temp);
@@ -127,32 +130,34 @@ static bool trans_movfcsr2gr(DisasContext *ctx, arg_movfcsr2gr *a)
 
     CHECK_FPE;
 
-    tcg_gen_ld32u_i64(dest, tcg_env, offsetof(CPULoongArchState, fcsr0));
-    tcg_gen_andi_i64(dest, dest, fcsr_mask[a->fcsrs]);
+    tcg_gen_ld32u_tl(dest, tcg_env, offsetof(CPULoongArchState, fcsr0));
+    tcg_gen_andi_tl(dest, dest, fcsr_mask[a->fcsrs]);
     gen_set_gpr(a->rd, dest, EXT_NONE);
 
     return true;
 }
 
-static void gen_movgr2fr_w(TCGv dest, TCGv src)
+static void gen_movgr2fr_w(TCGv_i64 dest, TCGv_i64 src)
 {
+
     tcg_gen_deposit_i64(dest, dest, src, 0, 32);
 }
 
-static void gen_movgr2frh_w(TCGv dest, TCGv src)
+static void gen_movgr2frh_w(TCGv_i64 dest, TCGv_i64 src)
 {
     tcg_gen_deposit_i64(dest, dest, src, 32, 32);
 }
 
-static void gen_movfrh2gr_s(TCGv dest, TCGv src)
+static void gen_movfrh2gr_s(TCGv_i64 dest, TCGv_i64 src)
 {
-    tcg_gen_sextract_tl(dest, src, 32, 32);
+    tcg_gen_sextract_i64(dest, src, 32, 32);
+    tcg_gen_ext32s_i64(dest, dest);
 }
 
 static bool trans_movfr2cf(DisasContext *ctx, arg_movfr2cf *a)
 {
-    TCGv t0;
-    TCGv src = get_fpr(ctx, a->fj);
+    TCGv_i64 t0;
+    TCGv_i64 src = get_fpr(ctx, a->fj);
 
     if (!avail_FP(ctx)) {
         return false;
@@ -160,16 +165,16 @@ static bool trans_movfr2cf(DisasContext *ctx, arg_movfr2cf *a)
 
     CHECK_FPE;
 
-    t0 = tcg_temp_new();
-    tcg_gen_andi_tl(t0, src, 0x1);
-    tcg_gen_st8_tl(t0, tcg_env, offsetof(CPULoongArchState, cf[a->cd & 0x7]));
+    t0 = tcg_temp_new_i64();
+    tcg_gen_andi_i64(t0, src, 0x1);
+    tcg_gen_st8_i64(t0, tcg_env, offsetof(CPULoongArchState, cf[a->cd & 0x7]));
 
     return true;
 }
 
 static bool trans_movcf2fr(DisasContext *ctx, arg_movcf2fr *a)
 {
-    TCGv dest = get_fpr(ctx, a->fd);
+    TCGv_i64 dest = get_fpr(ctx, a->fd);
 
     if (!avail_FP(ctx)) {
         return false;
@@ -177,7 +182,7 @@ static bool trans_movcf2fr(DisasContext *ctx, arg_movcf2fr *a)
 
     CHECK_FPE;
 
-    tcg_gen_ld8u_tl(dest, tcg_env,
+    tcg_gen_ld8u_i64(dest, tcg_env,
                     offsetof(CPULoongArchState, cf[a->cj & 0x7]));
     set_fpr(a->fd, dest);
 
@@ -214,11 +219,11 @@ static bool trans_movcf2gr(DisasContext *ctx, arg_movcf2gr *a)
     return true;
 }
 
-TRANS(fmov_s, FP_SP, gen_f2f, tcg_gen_mov_tl, true)
-TRANS(fmov_d, FP_DP, gen_f2f, tcg_gen_mov_tl, false)
+TRANS(fmov_s, FP_SP, gen_f2f, tcg_gen_mov_i64, true)
+TRANS(fmov_d, FP_DP, gen_f2f, tcg_gen_mov_i64, false)
 TRANS(movgr2fr_w, FP_SP, gen_r2f, gen_movgr2fr_w)
-TRANS(movgr2fr_d, 64, gen_r2f, tcg_gen_mov_tl)
+TRANS(movgr2fr_d, 64, gen_r2f, tcg_gen_mov_i64)
 TRANS(movgr2frh_w, FP_DP, gen_r2f, gen_movgr2frh_w)
-TRANS(movfr2gr_s, FP_SP, gen_f2r, tcg_gen_ext32s_tl)
-TRANS(movfr2gr_d, 64, gen_f2r, tcg_gen_mov_tl)
+TRANS(movfr2gr_s, FP_SP, gen_f2r, tcg_gen_ext32s_i64)
+TRANS(movfr2gr_d, 64, gen_f2r, tcg_gen_mov_i64)
 TRANS(movfrh2gr_s, FP_DP, gen_f2r, gen_movfrh2gr_s)
diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c
index 3939670e18d01bd9fc08861532166882fbd3f890..6494fac6aac04f495c18b4326bf271902d9df323 100644
--- a/target/loongarch/tcg/translate.c
+++ b/target/loongarch/tcg/translate.c
@@ -218,15 +218,15 @@ static void gen_set_gpr(int reg_num, TCGv t, DisasExtend dst_ext)
     }
 }
 
-static TCGv get_fpr(DisasContext *ctx, int reg_num)
+static TCGv_i64 get_fpr(DisasContext *ctx, int reg_num)
 {
-    TCGv t = tcg_temp_new();
+    TCGv_i64 t = tcg_temp_new_i64();
     tcg_gen_ld_i64(t, tcg_env,
                    offsetof(CPULoongArchState, fpr[reg_num].vreg.D(0)));
     return  t;
 }
 
-static void set_fpr(int reg_num, TCGv val)
+static void set_fpr(int reg_num, TCGv_i64 val)
 {
     tcg_gen_st_i64(val, tcg_env,
                    offsetof(CPULoongArchState, fpr[reg_num].vreg.D(0)));

-- 
2.43.0

[PATCH v2 11/23] target/loongarch: Scrutinise TCG vector translation for 32 bit build

[Jiaxun Yang]

Fix types for various TCGv.

Performing TCGv type conversion as necessary when interaction with GPR
happens.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/tcg/insn_trans/trans_vec.c.inc | 70 +++++++++++++------------
 1 file changed, 36 insertions(+), 34 deletions(-)

diff --git a/target/loongarch/tcg/insn_trans/trans_vec.c.inc b/target/loongarch/tcg/insn_trans/trans_vec.c.inc
index 92b1d22e28934b524a1f6ae6cb2bcbb189de27e3..e8015a332636d77ba72aeefde2e4135cdf2543a2 100644
--- a/target/loongarch/tcg/insn_trans/trans_vec.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_vec.c.inc
@@ -4761,7 +4761,8 @@ static bool trans_## NAME (DisasContext *ctx, arg_cv *a)                       \
                                                                                \
     tcg_gen_or_i64(t1, al, ah);                                                \
     tcg_gen_setcondi_i64(COND, t1, t1, 0);                                     \
-    tcg_gen_st8_tl(t1, tcg_env, offsetof(CPULoongArchState, cf[a->cd & 0x7])); \
+    tcg_gen_st8_i64(t1, tcg_env, offsetof(CPULoongArchState,                   \
+                                          cf[a->cd & 0x7]));                   \
                                                                                \
     return true;                                                               \
 }
@@ -4807,7 +4808,8 @@ static bool trans_## NAME(DisasContext *ctx, arg_cv * a)                       \
     tcg_gen_or_i64(t2, d[2], d[3]);                                            \
     tcg_gen_or_i64(t1, t2, t1);                                                \
     tcg_gen_setcondi_i64(COND, t1, t1, 0);                                     \
-    tcg_gen_st8_tl(t1, tcg_env, offsetof(CPULoongArchState, cf[a->cd & 0x7])); \
+    tcg_gen_st8_i64(t1, tcg_env, offsetof(CPULoongArchState,                   \
+                                          cf[a->cd & 0x7]));                   \
                                                                                \
     return true;                                                               \
 }
@@ -4850,12 +4852,12 @@ static bool gen_g2x(DisasContext *ctx, arg_vr_i *a, MemOp mop,
     return gen_g2v_vl(ctx, a, 32, mop, func);
 }
 
-TRANS(vinsgr2vr_b, LSX, gen_g2v, MO_8, tcg_gen_st8_i64)
-TRANS(vinsgr2vr_h, LSX, gen_g2v, MO_16, tcg_gen_st16_i64)
-TRANS(vinsgr2vr_w, LSX, gen_g2v, MO_32, tcg_gen_st32_i64)
-TRANS(vinsgr2vr_d, LSX, gen_g2v, MO_64, tcg_gen_st_i64)
-TRANS(xvinsgr2vr_w, LASX, gen_g2x, MO_32, tcg_gen_st32_i64)
-TRANS(xvinsgr2vr_d, LASX, gen_g2x, MO_64, tcg_gen_st_i64)
+TRANS(vinsgr2vr_b, LSX, gen_g2v, MO_8, tcg_gen_st8_tl)
+TRANS(vinsgr2vr_h, LSX, gen_g2v, MO_16, tcg_gen_st16_tl)
+TRANS(vinsgr2vr_w, LSX, gen_g2v, MO_32, tcg_gen_st32_tl)
+TRANS(vinsgr2vr_d, LSX, gen_g2v, MO_64, tcg_gen_st_tl)
+TRANS(xvinsgr2vr_w, LASX, gen_g2x, MO_32, tcg_gen_st32_tl)
+TRANS(xvinsgr2vr_d, LASX, gen_g2x, MO_64, tcg_gen_st_tl)
 
 static bool gen_v2g_vl(DisasContext *ctx, arg_rv_i *a, uint32_t oprsz, MemOp mop,
                        void (*func)(TCGv, TCGv_ptr, tcg_target_long))
@@ -4883,18 +4885,18 @@ static bool gen_x2g(DisasContext *ctx, arg_rv_i *a, MemOp mop,
     return gen_v2g_vl(ctx, a, 32, mop, func);
 }
 
-TRANS(vpickve2gr_b, LSX, gen_v2g, MO_8, tcg_gen_ld8s_i64)
-TRANS(vpickve2gr_h, LSX, gen_v2g, MO_16, tcg_gen_ld16s_i64)
-TRANS(vpickve2gr_w, LSX, gen_v2g, MO_32, tcg_gen_ld32s_i64)
-TRANS(vpickve2gr_d, LSX, gen_v2g, MO_64, tcg_gen_ld_i64)
-TRANS(vpickve2gr_bu, LSX, gen_v2g, MO_8, tcg_gen_ld8u_i64)
-TRANS(vpickve2gr_hu, LSX, gen_v2g, MO_16, tcg_gen_ld16u_i64)
-TRANS(vpickve2gr_wu, LSX, gen_v2g, MO_32, tcg_gen_ld32u_i64)
-TRANS(vpickve2gr_du, LSX, gen_v2g, MO_64, tcg_gen_ld_i64)
-TRANS(xvpickve2gr_w, LASX, gen_x2g, MO_32, tcg_gen_ld32s_i64)
-TRANS(xvpickve2gr_d, LASX, gen_x2g, MO_64, tcg_gen_ld_i64)
-TRANS(xvpickve2gr_wu, LASX, gen_x2g, MO_32, tcg_gen_ld32u_i64)
-TRANS(xvpickve2gr_du, LASX, gen_x2g, MO_64, tcg_gen_ld_i64)
+TRANS(vpickve2gr_b, LSX, gen_v2g, MO_8, tcg_gen_ld8s_tl)
+TRANS(vpickve2gr_h, LSX, gen_v2g, MO_16, tcg_gen_ld16s_tl)
+TRANS(vpickve2gr_w, LSX, gen_v2g, MO_32, tcg_gen_ld32s_tl)
+TRANS(vpickve2gr_d, LSX, gen_v2g, MO_64, tcg_gen_ld_tl)
+TRANS(vpickve2gr_bu, LSX, gen_v2g, MO_8, tcg_gen_ld8u_tl)
+TRANS(vpickve2gr_hu, LSX, gen_v2g, MO_16, tcg_gen_ld16u_tl)
+TRANS(vpickve2gr_wu, LSX, gen_v2g, MO_32, tcg_gen_ld32u_tl)
+TRANS(vpickve2gr_du, LSX, gen_v2g, MO_64, tcg_gen_ld_tl)
+TRANS(xvpickve2gr_w, LASX, gen_x2g, MO_32, tcg_gen_ld32s_tl)
+TRANS(xvpickve2gr_d, LASX, gen_x2g, MO_64, tcg_gen_ld_tl)
+TRANS(xvpickve2gr_wu, LASX, gen_x2g, MO_32, tcg_gen_ld32u_tl)
+TRANS(xvpickve2gr_du, LASX, gen_x2g, MO_64, tcg_gen_ld_tl)
 
 static bool gvec_dup_vl(DisasContext *ctx, arg_vr *a,
                         uint32_t oprsz, MemOp mop)
@@ -4905,8 +4907,8 @@ static bool gvec_dup_vl(DisasContext *ctx, arg_vr *a,
         return true;
     }
 
-    tcg_gen_gvec_dup_i64(mop, vec_full_offset(a->vd),
-                         oprsz, ctx->vl/8, src);
+    tcg_gen_gvec_dup_tl(mop, vec_full_offset(a->vd),
+                         oprsz, ctx->vl/TARGET_LONG_SIZE, src);
     return true;
 }
 
@@ -5007,8 +5009,8 @@ static bool gen_vreplve_vl(DisasContext *ctx, arg_vvr *a,
     if (!check_vec(ctx, oprsz)) {
         return true;
     }
-
-    tcg_gen_andi_i64(t0, gpr_src(ctx, a->rk, EXT_NONE), (LSX_LEN / bit) - 1);
+    tcg_gen_extu_tl_i64(t2, gpr_src(ctx, a->rk, EXT_NONE));
+    tcg_gen_andi_i64(t0, t2, (LSX_LEN / bit) - 1);
     tcg_gen_shli_i64(t0, t0, vece);
     if (HOST_BIG_ENDIAN) {
         tcg_gen_xori_i64(t0, t0, vece << ((LSX_LEN / bit) - 1));
@@ -5099,10 +5101,10 @@ static bool do_vbsll_v(DisasContext *ctx, arg_vv_i *a, uint32_t oprsz)
     }
 
     for (i = 0; i < oprsz / 16; i++) {
-        TCGv desthigh = tcg_temp_new_i64();
-        TCGv destlow = tcg_temp_new_i64();
-        TCGv high = tcg_temp_new_i64();
-        TCGv low = tcg_temp_new_i64();
+        TCGv_i64 desthigh = tcg_temp_new_i64();
+        TCGv_i64 destlow = tcg_temp_new_i64();
+        TCGv_i64 high = tcg_temp_new_i64();
+        TCGv_i64 low = tcg_temp_new_i64();
 
         get_vreg64(low, a->vj, 2 * i);
 
@@ -5131,10 +5133,10 @@ static bool do_vbsrl_v(DisasContext *ctx, arg_vv_i *a, uint32_t oprsz)
     }
 
     for (i = 0; i < oprsz / 16; i++) {
-        TCGv desthigh = tcg_temp_new_i64();
-        TCGv destlow = tcg_temp_new_i64();
-        TCGv high = tcg_temp_new_i64();
-        TCGv low = tcg_temp_new_i64();
+        TCGv_i64 desthigh = tcg_temp_new_i64();
+        TCGv_i64 destlow = tcg_temp_new_i64();
+        TCGv_i64 high = tcg_temp_new_i64();
+        TCGv_i64 low = tcg_temp_new_i64();
         get_vreg64(high, a->vj, 2 * i + 1);
 
         ofs = ((a->imm) & 0xf) * 8;
@@ -5459,7 +5461,7 @@ static void gen_xvld(DisasContext *ctx, int vreg, TCGv addr)
 {
     int i;
     TCGv temp = tcg_temp_new();
-    TCGv dest = tcg_temp_new();
+    TCGv_i64 dest = tcg_temp_new_i64();
 
     tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUQ);
     set_vreg64(dest, vreg, 0);
@@ -5475,7 +5477,7 @@ static void gen_xvst(DisasContext * ctx, int vreg, TCGv addr)
 {
     int i;
     TCGv temp = tcg_temp_new();
-    TCGv dest = tcg_temp_new();
+    TCGv_i64 dest = tcg_temp_new_i64();
 
     get_vreg64(dest, vreg, 0);
     tcg_gen_qemu_st_i64(dest, addr, ctx->mem_idx, MO_TEUQ);

-- 
2.43.0

[PATCH v2 12/23] target/loongarch: Scrutinise TCG bitops translation for 32 bit build

[Jiaxun Yang]

Use tl variant whenever possible.

Silent compiler warnings by performing casting for come consts.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/tcg/insn_trans/trans_bit.c.inc | 34 ++++++++++++++-----------
 1 file changed, 19 insertions(+), 15 deletions(-)

diff --git a/target/loongarch/tcg/insn_trans/trans_bit.c.inc b/target/loongarch/tcg/insn_trans/trans_bit.c.inc
index ee5fa003ce06a1910f826c3eb96d1d532c32e02c..a40346a670be31a123848e8ea5f7b94f8372976b 100644
--- a/target/loongarch/tcg/insn_trans/trans_bit.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_bit.c.inc
@@ -18,13 +18,17 @@ static bool gen_rr(DisasContext *ctx, arg_rr *a,
 
 static void gen_bytepick_w(TCGv dest, TCGv src1, TCGv src2, target_long sa)
 {
+#ifdef TARGET_LOONGARCH64
     tcg_gen_concat_tl_i64(dest, src1, src2);
     tcg_gen_sextract_i64(dest, dest, (32 - sa * 8), 32);
+#else
+    tcg_gen_extract2_tl(dest, src1, src2, (32 - sa * 8));
+#endif
 }
 
 static void gen_bytepick_d(TCGv dest, TCGv src1, TCGv src2, target_long sa)
 {
-    tcg_gen_extract2_i64(dest, src1, src2, (64 - sa * 8));
+    tcg_gen_extract2_tl(dest, src1, src2, (64 - sa * 8));
 }
 
 static bool gen_bstrins(DisasContext *ctx, arg_rr_ms_ls *a,
@@ -85,7 +89,7 @@ static void gen_cto_w(TCGv dest, TCGv src1)
 
 static void gen_clz_d(TCGv dest, TCGv src1)
 {
-    tcg_gen_clzi_i64(dest, src1, TARGET_LONG_BITS);
+    tcg_gen_clzi_tl(dest, src1, TARGET_LONG_BITS);
 }
 
 static void gen_clo_d(TCGv dest, TCGv src1)
@@ -107,8 +111,8 @@ static void gen_cto_d(TCGv dest, TCGv src1)
 
 static void gen_revb_2w(TCGv dest, TCGv src1)
 {
-    tcg_gen_bswap64_i64(dest, src1);
-    tcg_gen_rotri_i64(dest, dest, 32);
+    tcg_gen_bswap_tl(dest, src1);
+    tcg_gen_rotri_tl(dest, dest, 32);
 }
 
 static void gen_revb_2h(TCGv dest, TCGv src1)
@@ -126,7 +130,7 @@ static void gen_revb_2h(TCGv dest, TCGv src1)
 
 static void gen_revb_4h(TCGv dest, TCGv src1)
 {
-    TCGv mask = tcg_constant_tl(0x00FF00FF00FF00FFULL);
+    TCGv mask = tcg_constant_tl((target_ulong)0x00FF00FF00FF00FFULL);
     TCGv t0 = tcg_temp_new();
     TCGv t1 = tcg_temp_new();
 
@@ -139,22 +143,22 @@ static void gen_revb_4h(TCGv dest, TCGv src1)
 
 static void gen_revh_2w(TCGv dest, TCGv src1)
 {
-    TCGv_i64 t0 = tcg_temp_new_i64();
-    TCGv_i64 t1 = tcg_temp_new_i64();
-    TCGv_i64 mask = tcg_constant_i64(0x0000ffff0000ffffull);
+    TCGv t0 = tcg_temp_new();
+    TCGv t1 = tcg_temp_new();
+    TCGv mask = tcg_constant_tl((target_ulong)0x0000ffff0000ffffull);
 
-    tcg_gen_shri_i64(t0, src1, 16);
-    tcg_gen_and_i64(t1, src1, mask);
-    tcg_gen_and_i64(t0, t0, mask);
-    tcg_gen_shli_i64(t1, t1, 16);
-    tcg_gen_or_i64(dest, t1, t0);
+    tcg_gen_shri_tl(t0, src1, 16);
+    tcg_gen_and_tl(t1, src1, mask);
+    tcg_gen_and_tl(t0, t0, mask);
+    tcg_gen_shli_tl(t1, t1, 16);
+    tcg_gen_or_tl(dest, t1, t0);
 }
 
 static void gen_revh_d(TCGv dest, TCGv src1)
 {
     TCGv t0 = tcg_temp_new();
     TCGv t1 = tcg_temp_new();
-    TCGv mask = tcg_constant_tl(0x0000FFFF0000FFFFULL);
+    TCGv mask = tcg_constant_tl((target_ulong)0x0000FFFF0000FFFFULL);
 
     tcg_gen_shri_tl(t1, src1, 16);
     tcg_gen_and_tl(t1, t1, mask);
@@ -191,7 +195,7 @@ TRANS(ctz_d, 64, gen_rr, EXT_NONE, EXT_NONE, gen_ctz_d)
 TRANS(revb_2h, ALL, gen_rr, EXT_NONE, EXT_SIGN, gen_revb_2h)
 TRANS(revb_4h, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revb_4h)
 TRANS(revb_2w, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revb_2w)
-TRANS(revb_d, 64, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_bswap64_i64)
+TRANS(revb_d, 64, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_bswap_tl)
 TRANS(revh_2w, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revh_2w)
 TRANS(revh_d, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revh_d)
 TRANS(bitrev_4b, ALL, gen_rr, EXT_ZERO, EXT_SIGN, gen_helper_bitswap)

-- 
2.43.0

[PATCH v2 13/23] target/loongarch: Fix rdtimer on 32bit build

[Jiaxun Yang]

Use TCGv_i64 for intermediate values and perform truncation as necessary.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/tcg/insn_trans/trans_extra.c.inc | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/target/loongarch/tcg/insn_trans/trans_extra.c.inc b/target/loongarch/tcg/insn_trans/trans_extra.c.inc
index cfa361fecfa9ba569034b2c591b910ae7a3c6427..f9fb828ce51f2ee925edde7330d3054da534ecb3 100644
--- a/target/loongarch/tcg/insn_trans/trans_extra.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_extra.c.inc
@@ -46,13 +46,15 @@ static bool gen_rdtime(DisasContext *ctx, arg_rr *a,
 {
     TCGv dst1 = gpr_dst(ctx, a->rd, EXT_NONE);
     TCGv dst2 = gpr_dst(ctx, a->rj, EXT_NONE);
+    TCGv_i64 val = tcg_temp_new_i64();
 
     translator_io_start(&ctx->base);
-    gen_helper_rdtime_d(dst1, tcg_env);
+    gen_helper_rdtime_d(val, tcg_env);
     if (word) {
-        tcg_gen_sextract_tl(dst1, dst1, high ? 32 : 0, 32);
+        tcg_gen_sextract_i64(val, val, high ? 32 : 0, 32);
+        tcg_gen_trunc_i64_tl(dst1, val);
     }
-    tcg_gen_ld_i64(dst2, tcg_env, offsetof(CPULoongArchState, CSR_TID));
+    tcg_gen_ld_tl(dst2, tcg_env, offsetof(CPULoongArchState, CSR_TID));
 
     return true;
 }

-- 
2.43.0

[PATCH v2 14/23] target/loongarch: Scrutinise TCG arithmetic translation for 32 bit build

[Jiaxun Yang]

mulh.w and mulh.wu are handled with tcg_gen_muls2_i32 and tcg_gen_mulu2_i32
to adopt different TARGET_LONG size.

min value of divisor is generated from TARGET_LONG_BITS to adopt different
long size as well.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/tcg/insn_trans/trans_arith.c.inc | 25 +++++++++++++++++++----
 1 file changed, 21 insertions(+), 4 deletions(-)

diff --git a/target/loongarch/tcg/insn_trans/trans_arith.c.inc b/target/loongarch/tcg/insn_trans/trans_arith.c.inc
index 2be057e9320a9b722c173b0352e1631543147d68..a2360c5fdd2003ca0e458743348e687987f421d4 100644
--- a/target/loongarch/tcg/insn_trans/trans_arith.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_arith.c.inc
@@ -92,8 +92,24 @@ static void gen_sltu(TCGv dest, TCGv src1, TCGv src2)
 
 static void gen_mulh_w(TCGv dest, TCGv src1, TCGv src2)
 {
-    tcg_gen_mul_i64(dest, src1, src2);
-    tcg_gen_sari_i64(dest, dest, 32);
+#ifdef TARGET_LOONGARCH64
+    tcg_gen_mul_tl(dest, src1, src2);
+    tcg_gen_sari_tl(dest, dest, 32);
+#else
+    TCGv_i32 discard = tcg_temp_new_i32();
+    tcg_gen_muls2_i32(discard, dest, src1, src2);
+#endif
+}
+
+static void gen_mulh_wu(TCGv dest, TCGv src1, TCGv src2)
+{
+#ifdef TARGET_LOONGARCH64
+    /* Signs are handled by the caller's EXT_ZERO */
+    gen_mulh_w(dest, src1, src2);
+#else
+    TCGv_i32 discard = tcg_temp_new_i32();
+    tcg_gen_mulu2_i32(discard, dest, src1, src2);
+#endif
 }
 
 static void gen_mulh_d(TCGv dest, TCGv src1, TCGv src2)
@@ -113,6 +129,7 @@ static void prep_divisor_d(TCGv ret, TCGv src1, TCGv src2)
     TCGv t0 = tcg_temp_new();
     TCGv t1 = tcg_temp_new();
     TCGv zero = tcg_constant_tl(0);
+    target_long min = 1ull << (TARGET_LONG_BITS - 1);
 
     /*
      * If min / -1, set the divisor to 1.
@@ -121,7 +138,7 @@ static void prep_divisor_d(TCGv ret, TCGv src1, TCGv src2)
      * This avoids potential host overflow trap;
      * the required result is undefined.
      */
-    tcg_gen_setcondi_tl(TCG_COND_EQ, ret, src1, INT64_MIN);
+    tcg_gen_setcondi_tl(TCG_COND_EQ, ret, src1, min);
     tcg_gen_setcondi_tl(TCG_COND_EQ, t0, src2, -1);
     tcg_gen_setcondi_tl(TCG_COND_EQ, t1, src2, 0);
     tcg_gen_and_tl(ret, ret, t0);
@@ -275,7 +292,7 @@ TRANS(sltu, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sltu)
 TRANS(mul_w, ALL, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_SIGN, tcg_gen_mul_tl)
 TRANS(mul_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_mul_tl)
 TRANS(mulh_w, ALL, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_NONE, gen_mulh_w)
-TRANS(mulh_wu, ALL, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_NONE, gen_mulh_w)
+TRANS(mulh_wu, ALL, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_NONE, gen_mulh_wu)
 TRANS(mulh_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_mulh_d)
 TRANS(mulh_du, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_mulh_du)
 TRANS(mulw_d_w, 64, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_NONE, tcg_gen_mul_tl)

-- 
2.43.0

[PATCH v2 15/23] target/loongarch: Fix load type for gen_ll

[Jiaxun Yang]

gen_ll should use tcg_gen_qemu_ld_tl to load t1, as t1 is
in TCGv which means it should be a tl type value.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
index 8584441b543712af8a56aa234c90fd6370c8df01..138bcb3e9999b2c186057c658a019136311f1b82 100644
--- a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
@@ -9,7 +9,7 @@ static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop)
     TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
     TCGv t0 = make_address_i(ctx, src1, a->imm);
 
-    tcg_gen_qemu_ld_i64(t1, t0, ctx->mem_idx, mop);
+    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mop);
     tcg_gen_st_tl(t0, tcg_env, offsetof(CPULoongArchState, lladdr));
     tcg_gen_st_tl(t1, tcg_env, offsetof(CPULoongArchState, llval));
     gen_set_gpr(a->rd, t1, EXT_NONE);

-- 
2.43.0

[PATCH v2 16/23] target/loongarch: Define address space information for LoongArch32

[Jiaxun Yang]

LoongArch32 have 32 bit vaddr and 36 bit paddr as per architecture
specification.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/cpu-param.h | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h
index db5ad1c69fafaf368ad7f0c960afecb5a96ddcf2..48512883e550c80570eb2bf02c802f4979151008 100644
--- a/target/loongarch/cpu-param.h
+++ b/target/loongarch/cpu-param.h
@@ -8,9 +8,15 @@
 #ifndef LOONGARCH_CPU_PARAM_H
 #define LOONGARCH_CPU_PARAM_H
 
-#define TARGET_LONG_BITS 64
-#define TARGET_PHYS_ADDR_SPACE_BITS 48
-#define TARGET_VIRT_ADDR_SPACE_BITS 48
+#if defined(TARGET_LOONGARCH64)
+# define TARGET_LONG_BITS 64
+# define TARGET_PHYS_ADDR_SPACE_BITS 48
+# define TARGET_VIRT_ADDR_SPACE_BITS 48
+#elif defined(TARGET_LOONGARCH32)
+# define TARGET_LONG_BITS 32
+# define TARGET_PHYS_ADDR_SPACE_BITS 36
+# define TARGET_VIRT_ADDR_SPACE_BITS 32
+#endif
 
 #define TARGET_PAGE_BITS 12
 

-- 
2.43.0

[PATCH v2 17/23] target/loongarch: Refactoring is_la64/is_va32 for LoongArch32

[Jiaxun Yang]

is_la64 should be wired to false on LA32 build.
VA32 CSR check shouldn't be performed in LA32 mode.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/cpu.h | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 4f542a3376831141d012f177dc46a0e928afc85c..a2d416b6634b7f6787c93eac2b777a2f6c71bebf 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -438,18 +438,26 @@ struct LoongArchCPUClass {
 
 static inline bool is_la64(CPULoongArchState *env)
 {
+#ifdef TARGET_LOONGARCH64
     return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_LA64;
+#endif
+    return false;
 }
 
 static inline bool is_va32(CPULoongArchState *env)
 {
     /* VA32 if !LA64 or VA32L[1-3] */
-    bool va32 = !is_la64(env);
-    uint64_t plv = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
-    if (plv >= 1 && (FIELD_EX64(env->CSR_MISC, CSR_MISC, VA32) & (1 << plv))) {
-        va32 = true;
+    if (is_la64(env)) {
+        uint64_t plv = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
+
+        if (plv >= 1 &&
+            extract64(FIELD_EX64(env->CSR_MISC, CSR_MISC, VA32), plv, 1)) {
+            return true;
+        }
+        return false;
     }
-    return va32;
+
+    return true;
 }
 
 static inline void set_pc(CPULoongArchState *env, uint64_t value)

-- 
2.43.0

[PATCH v2 18/23] target/loongarch: ifdef out 64 bit CPUs on 32 bit builds

[Jiaxun Yang]

They are not available on 32 bit builds.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/cpu.c | 68 ++++++++++++++++++++++++++++----------------------
 1 file changed, 38 insertions(+), 30 deletions(-)

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 82412f8867a50a6cd25cff511def0f24d2b10b49..720f5b97698abe454c79c2f8fb2a36d0113c5c24 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -375,6 +375,36 @@ static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch)
     return MMU_DA_IDX;
 }
 
+static void loongarch_la132_initfn(Object *obj)
+{
+    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
+    CPULoongArchState *env = &cpu->env;
+
+    int i;
+
+    for (i = 0; i < 21; i++) {
+        env->cpucfg[i] = 0x0;
+    }
+
+    cpu->dtb_compatible = "loongarch,Loongson-1C103";
+    env->cpucfg[0] = 0x148042;  /* PRID */
+
+    uint32_t data = 0;
+    data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */
+    data = FIELD_DP32(data, CPUCFG1, PGMMU, 1);
+    data = FIELD_DP32(data, CPUCFG1, IOCSR, 1);
+    data = FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */
+    data = FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */
+    data = FIELD_DP32(data, CPUCFG1, UAL, 1);
+    data = FIELD_DP32(data, CPUCFG1, RI, 0);
+    data = FIELD_DP32(data, CPUCFG1, EP, 0);
+    data = FIELD_DP32(data, CPUCFG1, RPLV, 0);
+    data = FIELD_DP32(data, CPUCFG1, HP, 1);
+    data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1);
+    env->cpucfg[1] = data;
+}
+
+#ifdef TARGET_LOONGARCH64
 static void loongarch_la464_initfn(Object *obj)
 {
     LoongArchCPU *cpu = LOONGARCH_CPU(obj);
@@ -473,40 +503,12 @@ static void loongarch_la464_initfn(Object *obj)
     loongarch_cpu_post_init(obj);
 }
 
-static void loongarch_la132_initfn(Object *obj)
-{
-    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
-    CPULoongArchState *env = &cpu->env;
-
-    int i;
-
-    for (i = 0; i < 21; i++) {
-        env->cpucfg[i] = 0x0;
-    }
-
-    cpu->dtb_compatible = "loongarch,Loongson-1C103";
-    env->cpucfg[0] = 0x148042;  /* PRID */
-
-    uint32_t data = 0;
-    data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */
-    data = FIELD_DP32(data, CPUCFG1, PGMMU, 1);
-    data = FIELD_DP32(data, CPUCFG1, IOCSR, 1);
-    data = FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */
-    data = FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */
-    data = FIELD_DP32(data, CPUCFG1, UAL, 1);
-    data = FIELD_DP32(data, CPUCFG1, RI, 0);
-    data = FIELD_DP32(data, CPUCFG1, EP, 0);
-    data = FIELD_DP32(data, CPUCFG1, RPLV, 0);
-    data = FIELD_DP32(data, CPUCFG1, HP, 1);
-    data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1);
-    env->cpucfg[1] = data;
-}
-
 static void loongarch_max_initfn(Object *obj)
 {
     /* '-cpu max' for TCG: we use cpu la464. */
     loongarch_la464_initfn(obj);
 }
+#endif
 
 static void loongarch_cpu_reset_hold(Object *obj, ResetType type)
 {
@@ -870,6 +872,7 @@ static void loongarch32_cpu_class_init(ObjectClass *c, void *data)
     cc->gdb_arch_name = loongarch32_gdb_arch_name;
 }
 
+#ifdef TARGET_LOONGARCH64
 static const gchar *loongarch64_gdb_arch_name(CPUState *cs)
 {
     return "loongarch64";
@@ -882,6 +885,7 @@ static void loongarch64_cpu_class_init(ObjectClass *c, void *data)
     cc->gdb_core_xml_file = "loongarch-base64.xml";
     cc->gdb_arch_name = loongarch64_gdb_arch_name;
 }
+#endif
 
 #define DEFINE_LOONGARCH_CPU_TYPE(size, model, initfn) \
     { \
@@ -909,6 +913,7 @@ static const TypeInfo loongarch_cpu_type_infos[] = {
         .abstract = true,
         .class_init = loongarch32_cpu_class_init,
     },
+#ifdef TARGET_LOONGARCH64
     {
         .name = TYPE_LOONGARCH64_CPU,
         .parent = TYPE_LOONGARCH_CPU,
@@ -916,9 +921,12 @@ static const TypeInfo loongarch_cpu_type_infos[] = {
         .abstract = true,
         .class_init = loongarch64_cpu_class_init,
     },
-    DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn),
+#endif
     DEFINE_LOONGARCH_CPU_TYPE(32, "la132", loongarch_la132_initfn),
+#ifdef TARGET_LOONGARCH64
+    DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn),
     DEFINE_LOONGARCH_CPU_TYPE(64, "max", loongarch_max_initfn),
+#endif
 };
 
 DEFINE_TYPES(loongarch_cpu_type_infos)

-- 
2.43.0

[PATCH v2 19/23] target/loongarch: Introduce max32 CPU type

[Jiaxun Yang]

Introduce max32 CPU type as it's necessary to demonstrate all
features we have in LA32.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/cpu.c | 92 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 92 insertions(+)

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 720f5b97698abe454c79c2f8fb2a36d0113c5c24..afc6ff30b34af86c611c5866c9c79b3924c69ed7 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -404,6 +404,97 @@ static void loongarch_la132_initfn(Object *obj)
     env->cpucfg[1] = data;
 }
 
+static void loongarch_max32_initfn(Object *obj)
+{
+    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
+    CPULoongArchState *env = &cpu->env;
+    int i;
+
+    for (i = 0; i < 21; i++) {
+        env->cpucfg[i] = 0x0;
+    }
+
+    cpu->dtb_compatible = "loongarch,la32";
+    env->cpucfg[0] = 0x148042;  /* PRID */
+
+    uint32_t data = 0;
+    data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */
+    data = FIELD_DP32(data, CPUCFG1, PGMMU, 1);
+    data = FIELD_DP32(data, CPUCFG1, IOCSR, 1);
+    data = FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */
+    data = FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */
+    data = FIELD_DP32(data, CPUCFG1, UAL, 1);
+    data = FIELD_DP32(data, CPUCFG1, HP, 1);
+    data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1);
+    env->cpucfg[1] = data;
+
+    data = 0;
+    data = FIELD_DP32(data, CPUCFG2, FP, 1);
+    data = FIELD_DP32(data, CPUCFG2, FP_SP, 1);
+    data = FIELD_DP32(data, CPUCFG2, FP_DP, 1);
+    data = FIELD_DP32(data, CPUCFG2, FP_VER, 1);
+    data = FIELD_DP32(data, CPUCFG2, LLFTP, 1);
+    data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1);
+    env->cpucfg[2] = data;
+
+    data = 0;
+    data = FIELD_DP32(data, CPUCFG3, CCDMA, 1);
+    data = FIELD_DP32(data, CPUCFG3, ITLBHMC, 1);
+    data = FIELD_DP32(data, CPUCFG3, ICHMC, 1);
+    env->cpucfg[3] = data;
+
+    env->cpucfg[4] = 100 * 1000 * 1000; /* Crystal frequency */
+
+    data = 0;
+    data = FIELD_DP32(data, CPUCFG5, CC_MUL, 1);
+    data = FIELD_DP32(data, CPUCFG5, CC_DIV, 1);
+    env->cpucfg[5] = data;
+
+    data = 0;
+    data = FIELD_DP32(data, CPUCFG16, L1_IUPRE, 1);
+    data = FIELD_DP32(data, CPUCFG16, L1_DPRE, 1);
+    data = FIELD_DP32(data, CPUCFG16, L2_IUPRE, 1);
+    data = FIELD_DP32(data, CPUCFG16, L2_IUUNIFY, 1);
+    data = FIELD_DP32(data, CPUCFG16, L2_IUINCL, 1);
+    env->cpucfg[16] = data;
+
+    /* 16K L1I */
+    data = 0;
+    data = FIELD_DP32(data, CPUCFG17, L1IU_WAYS, 3);
+    data = FIELD_DP32(data, CPUCFG17, L1IU_SETS, 7);
+    data = FIELD_DP32(data, CPUCFG17, L1IU_SIZE, 5);
+    env->cpucfg[17] = data;
+
+    /* 16K L1D */
+    data = 0;
+    data = FIELD_DP32(data, CPUCFG18, L1D_WAYS, 3);
+    data = FIELD_DP32(data, CPUCFG18, L1D_SETS, 7);
+    data = FIELD_DP32(data, CPUCFG18, L1D_SIZE, 5);
+    env->cpucfg[18] = data;
+
+    data = 0;
+    /* 128K L2 */
+    data = FIELD_DP32(data, CPUCFG19, L2IU_WAYS, 7);
+    data = FIELD_DP32(data, CPUCFG19, L2IU_SETS, 9);
+    data = FIELD_DP32(data, CPUCFG19, L2IU_SIZE, 5);
+    env->cpucfg[19] = data;
+
+    env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa);
+
+    env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM, 8);
+    env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, TIMER_BITS, 31);
+    env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, VSMAX, 0);
+
+    env->CSR_PRCFG2 = 0x3ffff000;
+
+    env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2);
+    env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63);
+    env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7);
+    env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8);
+
+    loongarch_cpu_post_init(obj);
+}
+
 #ifdef TARGET_LOONGARCH64
 static void loongarch_la464_initfn(Object *obj)
 {
@@ -923,6 +1014,7 @@ static const TypeInfo loongarch_cpu_type_infos[] = {
     },
 #endif
     DEFINE_LOONGARCH_CPU_TYPE(32, "la132", loongarch_la132_initfn),
+    DEFINE_LOONGARCH_CPU_TYPE(32, "max32", loongarch_max32_initfn),
 #ifdef TARGET_LOONGARCH64
     DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn),
     DEFINE_LOONGARCH_CPU_TYPE(64, "max", loongarch_max_initfn),

-- 
2.43.0

[PATCH v2 20/23] hw/loongarch/virt: Default to max32 CPU for LoongArch 32 build

[Jiaxun Yang]

la464 CPU is not available on LoongArch32. Use max32 which makes
more sense here.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 hw/loongarch/virt.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 3a905cf71d46e3c5a29672f7bb73faedf1d29444..343d2e745e155d59f0ff17124b3c77ec9b3c111e 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -1440,7 +1440,11 @@ static void virt_class_init(ObjectClass *oc, void *data)
     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
 
     mc->init = virt_init;
+#if defined(TARGET_LOONGARCH64)
     mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464");
+#elif defined(TARGET_LOONGARCH32)
+    mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("max32");
+#endif
     mc->default_ram_id = "loongarch.ram";
     mc->desc = "QEMU LoongArch Virtual Machine";
     mc->max_cpus = LOONGARCH_MAX_CPUS;

-- 
2.43.0

[PATCH v2 21/23] qapi/machine: Replace TARGET_LOONGARCH64 with TARGET_LOONGARCH

[Jiaxun Yang]

All TARGET_LOONGARCH64 qapis are also available for LoongArch32 as we
are reusing the same CPU backend implemenation.

Use TARGET_LOONGARCH to identify LoongArch.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 qapi/machine-target.json | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/qapi/machine-target.json b/qapi/machine-target.json
index 541f93eeb78f67c7eac83d8a2722000976e38a33..b00c3f59b6a5f6e3ad9d7197d462e928ffc4c152 100644
--- a/qapi/machine-target.json
+++ b/qapi/machine-target.json
@@ -260,7 +260,7 @@
   'if': { 'any': [ 'TARGET_S390X',
                    'TARGET_I386',
                    'TARGET_ARM',
-                   'TARGET_LOONGARCH64',
+                   'TARGET_LOONGARCH',
                    'TARGET_RISCV' ] } }
 
 ##
@@ -314,7 +314,7 @@
   'if': { 'any': [ 'TARGET_S390X',
                    'TARGET_I386',
                    'TARGET_ARM',
-                   'TARGET_LOONGARCH64',
+                   'TARGET_LOONGARCH',
                    'TARGET_RISCV' ] } }
 
 ##
@@ -383,7 +383,7 @@
                    'TARGET_I386',
                    'TARGET_S390X',
                    'TARGET_MIPS',
-                   'TARGET_LOONGARCH64',
+                   'TARGET_LOONGARCH',
                    'TARGET_RISCV' ] } }
 
 ##
@@ -401,7 +401,7 @@
                    'TARGET_I386',
                    'TARGET_S390X',
                    'TARGET_MIPS',
-                   'TARGET_LOONGARCH64',
+                   'TARGET_LOONGARCH',
                    'TARGET_RISCV' ] } }
 
 ##

-- 
2.43.0

[PATCH v2 22/23] target/loongarch: Wire up LoongArch32 Kconfigs

[Jiaxun Yang]

Add LoongArch32 Kconfig entry and enable the virt machine for
LoongArch32.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 hw/loongarch/Kconfig     | 2 +-
 target/loongarch/Kconfig | 3 +++
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
index fe1c6feac13874424c110637067e5add26978833..fae467e3af1b7c7c6637f7ff04314bc09687c5dd 100644
--- a/hw/loongarch/Kconfig
+++ b/hw/loongarch/Kconfig
@@ -1,7 +1,7 @@
 config LOONGARCH_VIRT
     bool
     default y
-    depends on LOONGARCH64 && FDT
+    depends on (LOONGARCH32 || LOONGARCH64) && FDT
     select DEVICE_TREE
     select PCI
     select PCI_EXPRESS_GENERIC_BRIDGE
diff --git a/target/loongarch/Kconfig b/target/loongarch/Kconfig
index 46b26b1a85715e779672bea93152a3c62c170fe2..e428b066c6d09048d9a34803982e8f344237055d 100644
--- a/target/loongarch/Kconfig
+++ b/target/loongarch/Kconfig
@@ -1,2 +1,5 @@
+config LOONGARCH32
+    bool
+
 config LOONGARCH64
     bool

-- 
2.43.0

[PATCH v2 23/23] config: Add loongarch32-softmmu target

[Jiaxun Yang]

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 MAINTAINERS                                     | 4 ++--
 configs/devices/loongarch32-softmmu/default.mak | 7 +++++++
 configs/targets/loongarch32-softmmu.mak         | 7 +++++++
 3 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 8839f22e3ed306a598da1e4ab2f9f1899f574275..0c45d28508015d448c0b8a46cdb83e3974da2e28 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1210,8 +1210,8 @@ M: Bibo Mao <maobibo@loongson.cn>
 R: Jiaxun Yang <jiaxun.yang@flygoat.com>
 S: Maintained
 F: docs/system/loongarch/virt.rst
-F: configs/targets/loongarch64-softmmu.mak
-F: configs/devices/loongarch64-softmmu/default.mak
+F: configs/targets/loongarch*-softmmu.mak
+F: configs/devices/loongarch*-softmmu/default.mak
 F: hw/loongarch/
 F: include/hw/loongarch/virt.h
 F: include/hw/intc/loongarch_*.h
diff --git a/configs/devices/loongarch32-softmmu/default.mak b/configs/devices/loongarch32-softmmu/default.mak
new file mode 100644
index 0000000000000000000000000000000000000000..b28b5c7c9e2195cffe065716ee33ec2bf26e2b31
--- /dev/null
+++ b/configs/devices/loongarch32-softmmu/default.mak
@@ -0,0 +1,7 @@
+# Default configuration for loongarch32-softmmu
+
+# Uncomment the following lines to disable these optional devices:
+# CONFIG_PCI_DEVICES=n
+
+# Boards are selected by default, uncomment to keep out of the build.
+# CONFIG_LOONGARCH_VIRT=n
diff --git a/configs/targets/loongarch32-softmmu.mak b/configs/targets/loongarch32-softmmu.mak
new file mode 100644
index 0000000000000000000000000000000000000000..50e0075a24ac6bf3717db967b03b816b52a25964
--- /dev/null
+++ b/configs/targets/loongarch32-softmmu.mak
@@ -0,0 +1,7 @@
+TARGET_ARCH=loongarch32
+TARGET_BASE_ARCH=loongarch
+TARGET_KVM_HAVE_GUEST_DEBUG=y
+TARGET_SUPPORTS_MTTCG=y
+TARGET_XML_FILES= gdb-xml/loongarch-base32.xml gdb-xml/loongarch-fpu.xml gdb-xml/loongarch-lsx.xml gdb-xml/loongarch-lasx.xml
+# all boards require libfdt
+TARGET_NEED_FDT=y

-- 
2.43.0

Re: [PATCH v2 01/23] target/loongarch: Enable rotr.w/rotri.w for LoongArch32

[Richard Henderson]

On 12/26/24 13:19, Jiaxun Yang wrote:
> As per "LoongArch Reference Manual Volume 1: Basic Architecture" v1.1.0,
> "2.2 Table 2. Application-level basic integer instructions in LA32",
> rotr.w and rotri.w is a part of LA32 basic integer instructions.
> 
> Note that those instructions are indeed not in LA32R subset, however QEMU
> is not performing any check against LA32R so far.
> 
> Make it available to ALL.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>   target/loongarch/tcg/insn_trans/trans_shift.c.inc | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH v2 02/23] target/loongarch: Fix address generation for gen_sc

[Richard Henderson]

On 12/26/24 13:19, Jiaxun Yang wrote:
> gen_sc should use make_address_i to obtain source address
> to ensure that address is properly truncated.
> 
> Another temp value is created in middle to avoid data corruption
> as make_address_i may return the same memory location as src1.
> 
> Signed-off-by: Jiaxun Yang<jiaxun.yang@flygoat.com>
> ---
>   target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH v2 05/23] target/loongarch: Use target_ulong for iocsrrd helper results

[Richard Henderson]

On 12/26/24 13:19, Jiaxun Yang wrote:
> Those results are all targeting TCGv values, which means they should
> be in target_ulong type.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>   target/loongarch/helper.h           | 8 ++++----
>   target/loongarch/tcg/iocsr_helper.c | 8 ++++----
>   2 files changed, 8 insertions(+), 8 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH v2 07/23] target/loongarch: Cast address to 64bit before DMW_64_VSEG shift

[Richard Henderson]

On 12/26/24 13:19, Jiaxun Yang wrote:
> Avoid compiler warning on 32bit. This code path won't be taken anyway.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>   target/loongarch/cpu_helper.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c
> index 580362ac3e9ffbe6c8523cf57902dcda018ceed5..b8da136eb0554ba661a15e3069ee0d6bae61af86 100644
> --- a/target/loongarch/cpu_helper.c
> +++ b/target/loongarch/cpu_helper.c
> @@ -196,7 +196,7 @@ int get_physical_address(CPULoongArchState *env, hwaddr *physical,
>   
>       plv = kernel_mode | (user_mode << R_CSR_DMW_PLV3_SHIFT);
>       if (is_la64(env)) {
> -        base_v = address >> R_CSR_DMW_64_VSEG_SHIFT;
> +        base_v = (uint64_t)address >> R_CSR_DMW_64_VSEG_SHIFT;
>       } else {
>           base_v = address >> R_CSR_DMW_32_VSEG_SHIFT;
>       }
> 

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH v2 08/23] target/loongarch: Fix some modifiers for log formatting

[Richard Henderson]

On 12/26/24 13:19, Jiaxun Yang wrote:
> target_ulong -> TARGET_FMT_ld
> vaddr -> VADDR_PRIx
> uint32_t -> PRIx32
> 
> Signed-off-by: Jiaxun Yang<jiaxun.yang@flygoat.com>
> ---
>   target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
>   target/loongarch/tcg/tlb_helper.c                  | 2 +-
>   target/loongarch/tcg/translate.c                   | 5 ++---
>   3 files changed, 4 insertions(+), 5 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH v2 09/23] target/loongarch: Use target_ulong for CSR helpers

[Richard Henderson]

On 12/26/24 13:19, Jiaxun Yang wrote:
> All CSRs are meant to be target_ulong wide in our setting.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>   target/loongarch/helper.h        | 14 +++++++-------
>   target/loongarch/tcg/op_helper.c |  4 ++--
>   2 files changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
> index 409d93a5b0808f0e32b8c0e2e17cebac9feaf8ed..a608754b7f52689da9e9f4da1cef68d5af72f2ed 100644
> --- a/target/loongarch/helper.h
> +++ b/target/loongarch/helper.h
> @@ -97,13 +97,13 @@ DEF_HELPER_1(rdtime_d, i64, env)
>   
>   #ifndef CONFIG_USER_ONLY
>   /* CSRs helper */
> -DEF_HELPER_1(csrrd_pgd, i64, env)
> -DEF_HELPER_1(csrrd_cpuid, i64, env)
> -DEF_HELPER_1(csrrd_tval, i64, env)
> -DEF_HELPER_2(csrwr_estat, i64, env, tl)
> -DEF_HELPER_2(csrwr_asid, i64, env, tl)
> -DEF_HELPER_2(csrwr_tcfg, i64, env, tl)
> -DEF_HELPER_2(csrwr_ticlr, i64, env, tl)
> +DEF_HELPER_1(csrrd_pgd, tl, env)
> +DEF_HELPER_1(csrrd_cpuid, tl, env)
> +DEF_HELPER_1(csrrd_tval, tl, env)
> +DEF_HELPER_2(csrwr_estat, tl, env, tl)
> +DEF_HELPER_2(csrwr_asid, tl, env, tl)
> +DEF_HELPER_2(csrwr_tcfg, tl, env, tl)
> +DEF_HELPER_2(csrwr_ticlr, tl, env, tl)


Changes to helper declarations here, but not to definitions.


>   DEF_HELPER_2(iocsrrd_b, tl, env, tl)
>   DEF_HELPER_2(iocsrrd_h, tl, env, tl)
>   DEF_HELPER_2(iocsrrd_w, tl, env, tl)
> diff --git a/target/loongarch/tcg/op_helper.c b/target/loongarch/tcg/op_helper.c
> index b17208e5b962f2191b2afa60181bff311d618bba..c9d7e84e7ec9000bab655366bdf6ed8aaa4fd080 100644
> --- a/target/loongarch/tcg/op_helper.c
> +++ b/target/loongarch/tcg/op_helper.c
> @@ -61,7 +61,7 @@ void helper_asrtgt_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
>       }
>   }
>   
> -target_ulong helper_crc32(target_ulong val, target_ulong m, uint64_t sz)
> +target_ulong helper_crc32(target_ulong val, target_ulong m, target_ulong sz)
>   {
>       uint8_t buf[8];
>       target_ulong mask = ((sz * 8) == 64) ? -1ULL : ((1ULL << (sz * 8)) - 1);
> @@ -71,7 +71,7 @@ target_ulong helper_crc32(target_ulong val, target_ulong m, uint64_t sz)
>       return (int32_t) (crc32(val ^ 0xffffffff, buf, sz) ^ 0xffffffff);
>   }
>   
> -target_ulong helper_crc32c(target_ulong val, target_ulong m, uint64_t sz)
> +target_ulong helper_crc32c(target_ulong val, target_ulong m, target_ulong sz)
>   {
>       uint8_t buf[8];
>       target_ulong mask = ((sz * 8) == 64) ? -1ULL : ((1ULL << (sz * 8)) - 1);
> 

Changes to helper definitions, but not to the declarations.

Is this patch a victim of incorrect splitting, or incorrect rebasing?


r~

Re: [PATCH v2 09/23] target/loongarch: Use target_ulong for CSR helpers

[Jiaxun Yang]

在2024年12月26日十二月 下午9:31，Richard Henderson写道：
[...]
>>   
>> -target_ulong helper_crc32c(target_ulong val, target_ulong m, uint64_t sz)
>> +target_ulong helper_crc32c(target_ulong val, target_ulong m, target_ulong sz)
>>   {
>>       uint8_t buf[8];
>>       target_ulong mask = ((sz * 8) == 64) ? -1ULL : ((1ULL << (sz * 8)) - 1);
>> 
>
> Changes to helper definitions, but not to the declarations.
>
> Is this patch a victim of incorrect splitting, or incorrect rebasing?

Aha, those pairs of definitions and declarations are inconsistent in
existing code.

I should reflect this in commit message.

Thanks
>
>
> r~

-- 
- Jiaxun

Re: [PATCH v2 12/23] target/loongarch: Scrutinise TCG bitops translation for 32 bit build

[Richard Henderson]

On 12/26/24 13:19, Jiaxun Yang wrote:
> Use tl variant whenever possible.
> 
> Silent compiler warnings by performing casting for come consts.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>   target/loongarch/tcg/insn_trans/trans_bit.c.inc | 34 ++++++++++++++-----------
>   1 file changed, 19 insertions(+), 15 deletions(-)
> 
> diff --git a/target/loongarch/tcg/insn_trans/trans_bit.c.inc b/target/loongarch/tcg/insn_trans/trans_bit.c.inc
> index ee5fa003ce06a1910f826c3eb96d1d532c32e02c..a40346a670be31a123848e8ea5f7b94f8372976b 100644
> --- a/target/loongarch/tcg/insn_trans/trans_bit.c.inc
> +++ b/target/loongarch/tcg/insn_trans/trans_bit.c.inc
> @@ -18,13 +18,17 @@ static bool gen_rr(DisasContext *ctx, arg_rr *a,
>   
>   static void gen_bytepick_w(TCGv dest, TCGv src1, TCGv src2, target_long sa)
>   {
> +#ifdef TARGET_LOONGARCH64
>       tcg_gen_concat_tl_i64(dest, src1, src2);
>       tcg_gen_sextract_i64(dest, dest, (32 - sa * 8), 32);
> +#else
> +    tcg_gen_extract2_tl(dest, src1, src2, (32 - sa * 8));

This is the kind of case where using _i32 explicitly emphasizes that the specific size is 
required for correctness.  You've already got the ifdef to protect the code anyway.

>   static void gen_bytepick_d(TCGv dest, TCGv src1, TCGv src2, target_long sa)
>   {
> -    tcg_gen_extract2_i64(dest, src1, src2, (64 - sa * 8));
> +    tcg_gen_extract2_tl(dest, src1, src2, (64 - sa * 8));
>   }
>   
>   static bool gen_bstrins(DisasContext *ctx, arg_rr_ms_ls *a,
> @@ -85,7 +89,7 @@ static void gen_cto_w(TCGv dest, TCGv src1)
>   
>   static void gen_clz_d(TCGv dest, TCGv src1)
>   {
> -    tcg_gen_clzi_i64(dest, src1, TARGET_LONG_BITS);
> +    tcg_gen_clzi_tl(dest, src1, TARGET_LONG_BITS);
>   }
>   
>   static void gen_clo_d(TCGv dest, TCGv src1)
> @@ -107,8 +111,8 @@ static void gen_cto_d(TCGv dest, TCGv src1)
>   
>   static void gen_revb_2w(TCGv dest, TCGv src1)
>   {
> -    tcg_gen_bswap64_i64(dest, src1);
> -    tcg_gen_rotri_i64(dest, dest, 32);
> +    tcg_gen_bswap_tl(dest, src1);
> +    tcg_gen_rotri_tl(dest, dest, 32);
>   }
>   
>   static void gen_revb_2h(TCGv dest, TCGv src1)
> @@ -126,7 +130,7 @@ static void gen_revb_2h(TCGv dest, TCGv src1)
>   
>   static void gen_revb_4h(TCGv dest, TCGv src1)
>   {
> -    TCGv mask = tcg_constant_tl(0x00FF00FF00FF00FFULL);
> +    TCGv mask = tcg_constant_tl((target_ulong)0x00FF00FF00FF00FFULL);
>       TCGv t0 = tcg_temp_new();
>       TCGv t1 = tcg_temp_new();
>   
> @@ -139,22 +143,22 @@ static void gen_revb_4h(TCGv dest, TCGv src1)
>   
>   static void gen_revh_2w(TCGv dest, TCGv src1)
>   {
> -    TCGv_i64 t0 = tcg_temp_new_i64();
> -    TCGv_i64 t1 = tcg_temp_new_i64();
> -    TCGv_i64 mask = tcg_constant_i64(0x0000ffff0000ffffull);
> +    TCGv t0 = tcg_temp_new();
> +    TCGv t1 = tcg_temp_new();
> +    TCGv mask = tcg_constant_tl((target_ulong)0x0000ffff0000ffffull);
>   
> -    tcg_gen_shri_i64(t0, src1, 16);
> -    tcg_gen_and_i64(t1, src1, mask);
> -    tcg_gen_and_i64(t0, t0, mask);
> -    tcg_gen_shli_i64(t1, t1, 16);
> -    tcg_gen_or_i64(dest, t1, t0);
> +    tcg_gen_shri_tl(t0, src1, 16);
> +    tcg_gen_and_tl(t1, src1, mask);
> +    tcg_gen_and_tl(t0, t0, mask);
> +    tcg_gen_shli_tl(t1, t1, 16);
> +    tcg_gen_or_tl(dest, t1, t0);
>   }
>   
>   static void gen_revh_d(TCGv dest, TCGv src1)
>   {
>       TCGv t0 = tcg_temp_new();
>       TCGv t1 = tcg_temp_new();
> -    TCGv mask = tcg_constant_tl(0x0000FFFF0000FFFFULL);
> +    TCGv mask = tcg_constant_tl((target_ulong)0x0000FFFF0000FFFFULL);
>   
>       tcg_gen_shri_tl(t1, src1, 16);
>       tcg_gen_and_tl(t1, t1, mask);

While this allows the code to compile, (1) the functions are unused and (2) they do not 
compute the required results.  For me, the latter is concerning.

I'd suggest moving GEN_FALSE_TRANS out of trans_privileged.c.inc, then

#ifdef TARGET_LOONGARCH64
// all gen_foo_d
TRANS(bytepick_d, 64, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_d)
// etc
#else
GEN_FALSE_TRANS(bytepick_d)
// etc
#endif


r~

Re: [PATCH v2 14/23] target/loongarch: Scrutinise TCG arithmetic translation for 32 bit build

[Richard Henderson]

On 12/26/24 13:19, Jiaxun Yang wrote:
> mulh.w and mulh.wu are handled with tcg_gen_muls2_i32 and tcg_gen_mulu2_i32
> to adopt different TARGET_LONG size.
> 
> min value of divisor is generated from TARGET_LONG_BITS to adopt different
> long size as well.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>   target/loongarch/tcg/insn_trans/trans_arith.c.inc | 25 +++++++++++++++++++----
>   1 file changed, 21 insertions(+), 4 deletions(-)
> 
> diff --git a/target/loongarch/tcg/insn_trans/trans_arith.c.inc b/target/loongarch/tcg/insn_trans/trans_arith.c.inc
> index 2be057e9320a9b722c173b0352e1631543147d68..a2360c5fdd2003ca0e458743348e687987f421d4 100644
> --- a/target/loongarch/tcg/insn_trans/trans_arith.c.inc
> +++ b/target/loongarch/tcg/insn_trans/trans_arith.c.inc
> @@ -92,8 +92,24 @@ static void gen_sltu(TCGv dest, TCGv src1, TCGv src2)
>   
>   static void gen_mulh_w(TCGv dest, TCGv src1, TCGv src2)
>   {
> -    tcg_gen_mul_i64(dest, src1, src2);
> -    tcg_gen_sari_i64(dest, dest, 32);
> +#ifdef TARGET_LOONGARCH64
> +    tcg_gen_mul_tl(dest, src1, src2);
> +    tcg_gen_sari_tl(dest, dest, 32);

Leave the _i64.

> +#else
> +    TCGv_i32 discard = tcg_temp_new_i32();
> +    tcg_gen_muls2_i32(discard, dest, src1, src2);
> +#endif
> +}
> +
> +static void gen_mulh_wu(TCGv dest, TCGv src1, TCGv src2)
> +{
> +#ifdef TARGET_LOONGARCH64
> +    /* Signs are handled by the caller's EXT_ZERO */
> +    gen_mulh_w(dest, src1, src2);
> +#else
> +    TCGv_i32 discard = tcg_temp_new_i32();
> +    tcg_gen_mulu2_i32(discard, dest, src1, src2);
> +#endif
>   }

Otherwise, these two are fine.

>   
>   static void gen_mulh_d(TCGv dest, TCGv src1, TCGv src2)
> @@ -113,6 +129,7 @@ static void prep_divisor_d(TCGv ret, TCGv src1, TCGv src2)
>       TCGv t0 = tcg_temp_new();
>       TCGv t1 = tcg_temp_new();
>       TCGv zero = tcg_constant_tl(0);
> +    target_long min = 1ull << (TARGET_LONG_BITS - 1);
>   
>       /*
>        * If min / -1, set the divisor to 1.
> @@ -121,7 +138,7 @@ static void prep_divisor_d(TCGv ret, TCGv src1, TCGv src2)
>        * This avoids potential host overflow trap;
>        * the required result is undefined.
>        */
> -    tcg_gen_setcondi_tl(TCG_COND_EQ, ret, src1, INT64_MIN);
> +    tcg_gen_setcondi_tl(TCG_COND_EQ, ret, src1, min);
>       tcg_gen_setcondi_tl(TCG_COND_EQ, t0, src2, -1);
>       tcg_gen_setcondi_tl(TCG_COND_EQ, t1, src2, 0);
>       tcg_gen_and_tl(ret, ret, t0);

This is ok, but s/prep_divisor_d/prep_divisor_tl/.
Without the rename, this change would appear to affect correctness.

In addition, gen_{div,rem}_w will need to use prep_divisor_tl instead of prep_divisor_du.


r~

Re: [PATCH v2 15/23] target/loongarch: Fix load type for gen_ll

[Richard Henderson]

On 12/26/24 13:19, Jiaxun Yang wrote:
> gen_ll should use tcg_gen_qemu_ld_tl to load t1, as t1 is
> in TCGv which means it should be a tl type value.
> 
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>   target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
> index 8584441b543712af8a56aa234c90fd6370c8df01..138bcb3e9999b2c186057c658a019136311f1b82 100644
> --- a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
> +++ b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
> @@ -9,7 +9,7 @@ static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop)
>       TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
>       TCGv t0 = make_address_i(ctx, src1, a->imm);
>   
> -    tcg_gen_qemu_ld_i64(t1, t0, ctx->mem_idx, mop);
> +    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mop);
>       tcg_gen_st_tl(t0, tcg_env, offsetof(CPULoongArchState, lladdr));
>       tcg_gen_st_tl(t1, tcg_env, offsetof(CPULoongArchState, llval));
>       gen_set_gpr(a->rd, t1, EXT_NONE);
> 

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH v2 12/23] target/loongarch: Scrutinise TCG bitops translation for 32 bit build

[Jiaxun Yang]

在2024年12月26日十二月 下午9:55，Richard Henderson写道：
[...]
> While this allows the code to compile, (1) the functions are unused and 
> (2) they do not 
> compute the required results.  For me, the latter is concerning.
>
> I'd suggest moving GEN_FALSE_TRANS out of trans_privileged.c.inc, then
>
> #ifdef TARGET_LOONGARCH64
> // all gen_foo_d
> TRANS(bytepick_d, 64, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_d)
> // etc
> #else
> GEN_FALSE_TRANS(bytepick_d)
> // etc
> #endif

Thanks for the insight!

I'm actually thinking about introducing an TRANS64 which resolves to
GEN_FALSE_TRANS if not on TARGET_LOONGARCH64.

Will try in next version.

Thanks
>
>
> r~

-- 
- Jiaxun

Re: [PATCH v2 12/23] target/loongarch: Scrutinise TCG bitops translation for 32 bit build

[Richard Henderson]

On 12/26/24 14:08, Jiaxun Yang wrote:
> 
> 
> 在2024年12月26日十二月 下午9:55，Richard Henderson写道：
> [...]
>> While this allows the code to compile, (1) the functions are unused and
>> (2) they do not
>> compute the required results.  For me, the latter is concerning.
>>
>> I'd suggest moving GEN_FALSE_TRANS out of trans_privileged.c.inc, then
>>
>> #ifdef TARGET_LOONGARCH64
>> // all gen_foo_d
>> TRANS(bytepick_d, 64, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_d)
>> // etc
>> #else
>> GEN_FALSE_TRANS(bytepick_d)
>> // etc
>> #endif
> 
> Thanks for the insight!
> 
> I'm actually thinking about introducing an TRANS64 which resolves to
> GEN_FALSE_TRANS if not on TARGET_LOONGARCH64.

That works too!


r~

Re: [PATCH v2 10/23] target/loongarch: Scrutinise TCG float translation for 32 bit build

[Richard Henderson]

On 12/26/24 13:19, Jiaxun Yang wrote:
> All float computations are kept to be 64 bit, fix types for various TCGv.
> 
> Performing TCGv type conversion as necessary when interaction with GPR
> happens.
> 
> Signed-off-by: Jiaxun Yang<jiaxun.yang@flygoat.com>
> ---
>   target/loongarch/tcg/insn_trans/trans_farith.c.inc | 53 +++++++-------
>   target/loongarch/tcg/insn_trans/trans_fcmp.c.inc   | 16 ++---
>   .../loongarch/tcg/insn_trans/trans_fmemory.c.inc   | 34 ++++-----
>   target/loongarch/tcg/insn_trans/trans_fmov.c.inc   | 83 ++++++++++++----------
>   target/loongarch/tcg/translate.c                   |  6 +-
>   5 files changed, 99 insertions(+), 93 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH v2 13/23] target/loongarch: Fix rdtimer on 32bit build

[Richard Henderson]

On 12/26/24 13:19, Jiaxun Yang wrote:
> Use TCGv_i64 for intermediate values and perform truncation as necessary.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>   target/loongarch/tcg/insn_trans/trans_extra.c.inc | 8 +++++---
>   1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/target/loongarch/tcg/insn_trans/trans_extra.c.inc b/target/loongarch/tcg/insn_trans/trans_extra.c.inc
> index cfa361fecfa9ba569034b2c591b910ae7a3c6427..f9fb828ce51f2ee925edde7330d3054da534ecb3 100644
> --- a/target/loongarch/tcg/insn_trans/trans_extra.c.inc
> +++ b/target/loongarch/tcg/insn_trans/trans_extra.c.inc
> @@ -46,13 +46,15 @@ static bool gen_rdtime(DisasContext *ctx, arg_rr *a,
>   {
>       TCGv dst1 = gpr_dst(ctx, a->rd, EXT_NONE);
>       TCGv dst2 = gpr_dst(ctx, a->rj, EXT_NONE);
> +    TCGv_i64 val = tcg_temp_new_i64();
>   
>       translator_io_start(&ctx->base);
> -    gen_helper_rdtime_d(dst1, tcg_env);
> +    gen_helper_rdtime_d(val, tcg_env);
>       if (word) {
> -        tcg_gen_sextract_tl(dst1, dst1, high ? 32 : 0, 32);
> +        tcg_gen_sextract_i64(val, val, high ? 32 : 0, 32);
> +        tcg_gen_trunc_i64_tl(dst1, val);
>       }

If !word, you are no longer assigning to dst1.
The trunc must be moved below if (word).


r~

Re: [PATCH v2 11/23] target/loongarch: Scrutinise TCG vector translation for 32 bit build

[Richard Henderson]

On 12/26/24 13:19, Jiaxun Yang wrote:
> @@ -4850,12 +4852,12 @@ static bool gen_g2x(DisasContext *ctx, arg_vr_i *a, MemOp mop,
>       return gen_g2v_vl(ctx, a, 32, mop, func);
>   }
>   
> -TRANS(vinsgr2vr_b, LSX, gen_g2v, MO_8, tcg_gen_st8_i64)
> -TRANS(vinsgr2vr_h, LSX, gen_g2v, MO_16, tcg_gen_st16_i64)
> -TRANS(vinsgr2vr_w, LSX, gen_g2v, MO_32, tcg_gen_st32_i64)
> -TRANS(vinsgr2vr_d, LSX, gen_g2v, MO_64, tcg_gen_st_i64)
> -TRANS(xvinsgr2vr_w, LASX, gen_g2x, MO_32, tcg_gen_st32_i64)
> -TRANS(xvinsgr2vr_d, LASX, gen_g2x, MO_64, tcg_gen_st_i64)
> +TRANS(vinsgr2vr_b, LSX, gen_g2v, MO_8, tcg_gen_st8_tl)
> +TRANS(vinsgr2vr_h, LSX, gen_g2v, MO_16, tcg_gen_st16_tl)
> +TRANS(vinsgr2vr_w, LSX, gen_g2v, MO_32, tcg_gen_st32_tl)
> +TRANS(vinsgr2vr_d, LSX, gen_g2v, MO_64, tcg_gen_st_tl)
> +TRANS(xvinsgr2vr_w, LASX, gen_g2x, MO_32, tcg_gen_st32_tl)
> +TRANS(xvinsgr2vr_d, LASX, gen_g2x, MO_64, tcg_gen_st_tl)

All of these *_d instructions are invalid for LA32.
This is obvious because they specifically refer to general registers.

All of the rest of these changes need to be audited.

> @@ -4905,8 +4907,8 @@ static bool gvec_dup_vl(DisasContext *ctx, arg_vr *a,
>           return true;
>       }
>   
> -    tcg_gen_gvec_dup_i64(mop, vec_full_offset(a->vd),
> -                         oprsz, ctx->vl/8, src);
> +    tcg_gen_gvec_dup_tl(mop, vec_full_offset(a->vd),
> +                         oprsz, ctx->vl/TARGET_LONG_SIZE, src);
>       return true;
>   }

This is not obvious.  There might be uses for which we really ought to have extended the 
src argument to TCGv_i64.


r~

Re: [PATCH v2 05/23] target/loongarch: Use target_ulong for iocsrrd helper results

[Philippe Mathieu-Daudé]

On 26/12/24 22:19, Jiaxun Yang wrote:
> Those results are all targeting TCGv values, which means they should
> be in target_ulong type.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>   target/loongarch/helper.h           | 8 ++++----
>   target/loongarch/tcg/iocsr_helper.c | 8 ++++----
>   2 files changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
> index b3b64a021536255a3f9decfc10ff61fe8380e2ae..409d93a5b0808f0e32b8c0e2e17cebac9feaf8ed 100644
> --- a/target/loongarch/helper.h
> +++ b/target/loongarch/helper.h
> @@ -104,10 +104,10 @@ DEF_HELPER_2(csrwr_estat, i64, env, tl)
>   DEF_HELPER_2(csrwr_asid, i64, env, tl)
>   DEF_HELPER_2(csrwr_tcfg, i64, env, tl)
>   DEF_HELPER_2(csrwr_ticlr, i64, env, tl)
> -DEF_HELPER_2(iocsrrd_b, i64, env, tl)
> -DEF_HELPER_2(iocsrrd_h, i64, env, tl)
> -DEF_HELPER_2(iocsrrd_w, i64, env, tl)
> -DEF_HELPER_2(iocsrrd_d, i64, env, tl)
> +DEF_HELPER_2(iocsrrd_b, tl, env, tl)
> +DEF_HELPER_2(iocsrrd_h, tl, env, tl)
> +DEF_HELPER_2(iocsrrd_w, tl, env, tl)
> +DEF_HELPER_2(iocsrrd_d, tl, env, tl)
>   DEF_HELPER_3(iocsrwr_b, void, env, tl, tl)
>   DEF_HELPER_3(iocsrwr_h, void, env, tl, tl)
>   DEF_HELPER_3(iocsrwr_w, void, env, tl, tl)
> diff --git a/target/loongarch/tcg/iocsr_helper.c b/target/loongarch/tcg/iocsr_helper.c
> index db30de2523fff01bcc8923eb12c7fca7bedca7bf..23d819de0ef9790eb82741f1e8a0e20dc139bf4b 100644
> --- a/target/loongarch/tcg/iocsr_helper.c
> +++ b/target/loongarch/tcg/iocsr_helper.c
> @@ -15,25 +15,25 @@
>   #define GET_MEMTXATTRS(cas) \
>           ((MemTxAttrs){.requester_id = env_cpu(cas)->cpu_index})
>   
> -uint64_t helper_iocsrrd_b(CPULoongArchState *env, target_ulong r_addr)
> +target_ulong helper_iocsrrd_b(CPULoongArchState *env, target_ulong r_addr)
>   {
>       return (int8_t)address_space_ldub(env->address_space_iocsr, r_addr,
>                                         GET_MEMTXATTRS(env), NULL);
>   }
>   
> -uint64_t helper_iocsrrd_h(CPULoongArchState *env, target_ulong r_addr)
> +target_ulong helper_iocsrrd_h(CPULoongArchState *env, target_ulong r_addr)
>   {
>       return (int16_t)address_space_lduw(env->address_space_iocsr, r_addr,
>                                          GET_MEMTXATTRS(env), NULL);
>   }
>   
> -uint64_t helper_iocsrrd_w(CPULoongArchState *env, target_ulong r_addr)
> +target_ulong helper_iocsrrd_w(CPULoongArchState *env, target_ulong r_addr)
>   {
>       return (int32_t)address_space_ldl(env->address_space_iocsr, r_addr,
>                                         GET_MEMTXATTRS(env), NULL);
>   }
>   
> -uint64_t helper_iocsrrd_d(CPULoongArchState *env, target_ulong r_addr)
> +target_ulong helper_iocsrrd_d(CPULoongArchState *env, target_ulong r_addr)
>   {
>       return address_space_ldq(env->address_space_iocsr, r_addr,
>                                GET_MEMTXATTRS(env), NULL);
> 

We could reduce code duplication adding address_space_ldn().

Anyhow, for this patch:
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Re: [PATCH v2 06/23] target/loongarch: Store some uint64_t values as target_ulong

[Philippe Mathieu-Daudé]

On 26/12/24 22:19, Jiaxun Yang wrote:
> Store internal registers including GPRs, CSRs, and LBT scratchs
> as target_ulong, as per architecture specification.
> 
> The only exception here is tlb_misc, as it's only used by QEMU
> internally and need keep to be 64bit to store all required fields.
> 
> There is no migration ABI change, as target_ulong is uint64_t on
> existing loongarch64 builds anyway.

I'm working on a prototype series where target_ulong becomes uint64_t
under TCG. This patch is going the opposite direction. Not sure what
to say at this point (I'm not rejecting it, just wondering).

> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>   target/loongarch/cpu.c     |  34 ++++++------
>   target/loongarch/cpu.h     | 132 ++++++++++++++++++++++-----------------------
>   target/loongarch/machine.c | 120 ++++++++++++++++++++---------------------
>   3 files changed, 143 insertions(+), 143 deletions(-)

Re: [PATCH v2 08/23] target/loongarch: Fix some modifiers for log formatting

[Philippe Mathieu-Daudé]

On 26/12/24 22:19, Jiaxun Yang wrote:
> target_ulong -> TARGET_FMT_ld
> vaddr -> VADDR_PRIx
> uint32_t -> PRIx32
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>   target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
>   target/loongarch/tcg/tlb_helper.c                  | 2 +-
>   target/loongarch/tcg/translate.c                   | 5 ++---
>   3 files changed, 4 insertions(+), 5 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Re: [PATCH v2 19/23] target/loongarch: Introduce max32 CPU type

[Philippe Mathieu-Daudé]

On 26/12/24 22:19, Jiaxun Yang wrote:
> Introduce max32 CPU type as it's necessary to demonstrate all
> features we have in LA32.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>   target/loongarch/cpu.c | 92 ++++++++++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 92 insertions(+)


>   #ifdef TARGET_LOONGARCH64
>   static void loongarch_la464_initfn(Object *obj)
>   {
> @@ -923,6 +1014,7 @@ static const TypeInfo loongarch_cpu_type_infos[] = {
>       },
>   #endif
>       DEFINE_LOONGARCH_CPU_TYPE(32, "la132", loongarch_la132_initfn),
> +    DEFINE_LOONGARCH_CPU_TYPE(32, "max32", loongarch_max32_initfn),

What about "la32max"?

>   #ifdef TARGET_LOONGARCH64
>       DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn),
>       DEFINE_LOONGARCH_CPU_TYPE(64, "max", loongarch_max_initfn),
> 

Re: [PATCH v2 20/23] hw/loongarch/virt: Default to max32 CPU for LoongArch 32 build

[Philippe Mathieu-Daudé]

On 26/12/24 22:19, Jiaxun Yang wrote:
> la464 CPU is not available on LoongArch32. Use max32 which makes
> more sense here.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>   hw/loongarch/virt.c | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
> index 3a905cf71d46e3c5a29672f7bb73faedf1d29444..343d2e745e155d59f0ff17124b3c77ec9b3c111e 100644
> --- a/hw/loongarch/virt.c
> +++ b/hw/loongarch/virt.c
> @@ -1440,7 +1440,11 @@ static void virt_class_init(ObjectClass *oc, void *data)
>       HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
>   
>       mc->init = virt_init;
> +#if defined(TARGET_LOONGARCH64)
>       mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464");
> +#elif defined(TARGET_LOONGARCH32)
> +    mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("max32");

Why can't we use it on LOONGARCH64?

> +#endif
>       mc->default_ram_id = "loongarch.ram";
>       mc->desc = "QEMU LoongArch Virtual Machine";
>       mc->max_cpus = LOONGARCH_MAX_CPUS;
> 

Re: [PATCH v2 06/23] target/loongarch: Store some uint64_t values as target_ulong

[Jiaxun Yang]

在2024年12月26日十二月 下午10:48，Philippe Mathieu-Daudé写道：
> On 26/12/24 22:19, Jiaxun Yang wrote:
>> Store internal registers including GPRs, CSRs, and LBT scratchs
>> as target_ulong, as per architecture specification.
>> 
>> The only exception here is tlb_misc, as it's only used by QEMU
>> internally and need keep to be 64bit to store all required fields.
>> 
>> There is no migration ABI change, as target_ulong is uint64_t on
>> existing loongarch64 builds anyway.
>
> I'm working on a prototype series where target_ulong becomes uint64_t
> under TCG. This patch is going the opposite direction. Not sure what
> to say at this point (I'm not rejecting it, just wondering).

Does this mean TCGv will always be 64bit?

I'm doing this just to keep all TCG _tl load/store sane. If that's the
way to go, I'm happy to adopt full uint64_t approach.

Thanks
>
>> 
>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> ---
>>   target/loongarch/cpu.c     |  34 ++++++------
>>   target/loongarch/cpu.h     | 132 ++++++++++++++++++++++-----------------------
>>   target/loongarch/machine.c | 120 ++++++++++++++++++++---------------------
>>   3 files changed, 143 insertions(+), 143 deletions(-)

-- 
- Jiaxun

Re: [PATCH v2 23/23] config: Add loongarch32-softmmu target

[Philippe Mathieu-Daudé]

On 26/12/24 22:19, Jiaxun Yang wrote:
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>   MAINTAINERS                                     | 4 ++--
>   configs/devices/loongarch32-softmmu/default.mak | 7 +++++++
>   configs/targets/loongarch32-softmmu.mak         | 7 +++++++
>   3 files changed, 16 insertions(+), 2 deletions(-)


> diff --git a/configs/targets/loongarch32-softmmu.mak b/configs/targets/loongarch32-softmmu.mak
> new file mode 100644
> index 0000000000000000000000000000000000000000..50e0075a24ac6bf3717db967b03b816b52a25964
> --- /dev/null
> +++ b/configs/targets/loongarch32-softmmu.mak
> @@ -0,0 +1,7 @@
> +TARGET_ARCH=loongarch32
> +TARGET_BASE_ARCH=loongarch
> +TARGET_KVM_HAVE_GUEST_DEBUG=y
> +TARGET_SUPPORTS_MTTCG=y
> +TARGET_XML_FILES= gdb-xml/loongarch-base32.xml gdb-xml/loongarch-fpu.xml gdb-xml/loongarch-lsx.xml gdb-xml/loongarch-lasx.xml
> +# all boards require libfdt
> +TARGET_NEED_FDT=y
> 

I'd really like, if possible, to not add a new target, but make the
current loongarch64-softmmu.mak evolve to support both 32/64 modes.

Re: [PATCH v2 19/23] target/loongarch: Introduce max32 CPU type

[Jiaxun Yang]

在2024年12月26日十二月 下午10:55，Philippe Mathieu-Daudé写道：
> On 26/12/24 22:19, Jiaxun Yang wrote:
>> Introduce max32 CPU type as it's necessary to demonstrate all
>> features we have in LA32.
>> 
>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> ---
>>   target/loongarch/cpu.c | 92 ++++++++++++++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 92 insertions(+)
>
>
>>   #ifdef TARGET_LOONGARCH64
>>   static void loongarch_la464_initfn(Object *obj)
>>   {
>> @@ -923,6 +1014,7 @@ static const TypeInfo loongarch_cpu_type_infos[] = {
>>       },
>>   #endif
>>       DEFINE_LOONGARCH_CPU_TYPE(32, "la132", loongarch_la132_initfn),
>> +    DEFINE_LOONGARCH_CPU_TYPE(32, "max32", loongarch_max32_initfn),
>
> What about "la32max"?

I'm actually thinking about "max32" for la32 and "max32r" la32r to keep it concise
(and somehow aligned with existing RISC-V naming).

Thanks
>
>>   #ifdef TARGET_LOONGARCH64
>>       DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn),
>>       DEFINE_LOONGARCH_CPU_TYPE(64, "max", loongarch_max_initfn),
>>

-- 
- Jiaxun

Re: [PATCH v2 06/23] target/loongarch: Store some uint64_t values as target_ulong

[Philippe Mathieu-Daudé]

On 26/12/24 23:58, Jiaxun Yang wrote:
> 
> 
> 在2024年12月26日十二月 下午10:48，Philippe Mathieu-Daudé写道：
>> On 26/12/24 22:19, Jiaxun Yang wrote:
>>> Store internal registers including GPRs, CSRs, and LBT scratchs
>>> as target_ulong, as per architecture specification.
>>>
>>> The only exception here is tlb_misc, as it's only used by QEMU
>>> internally and need keep to be 64bit to store all required fields.
>>>
>>> There is no migration ABI change, as target_ulong is uint64_t on
>>> existing loongarch64 builds anyway.
>>
>> I'm working on a prototype series where target_ulong becomes uint64_t
>> under TCG. This patch is going the opposite direction. Not sure what
>> to say at this point (I'm not rejecting it, just wondering).
> 
> Does this mean TCGv will always be 64bit?
> 
> I'm doing this just to keep all TCG _tl load/store sane. If that's the
> way to go, I'm happy to adopt full uint64_t approach.

"full uint64_t approach" won't happen before months (except if we get
more manpower).

The idea is to add all current generic TCG ops but taking an extra MemOp
argument, having the backend sign-extending / truncating.

Re: [PATCH v2 20/23] hw/loongarch/virt: Default to max32 CPU for LoongArch 32 build

[Jiaxun Yang]

在2024年12月26日十二月 下午10:56，Philippe Mathieu-Daudé写道：
> On 26/12/24 22:19, Jiaxun Yang wrote:
>> la464 CPU is not available on LoongArch32. Use max32 which makes
>> more sense here.
>> 
>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> ---
>>   hw/loongarch/virt.c | 4 ++++
>>   1 file changed, 4 insertions(+)
>> 
>> diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
>> index 3a905cf71d46e3c5a29672f7bb73faedf1d29444..343d2e745e155d59f0ff17124b3c77ec9b3c111e 100644
>> --- a/hw/loongarch/virt.c
>> +++ b/hw/loongarch/virt.c
>> @@ -1440,7 +1440,11 @@ static void virt_class_init(ObjectClass *oc, void *data)
>>       HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
>>   
>>       mc->init = virt_init;
>> +#if defined(TARGET_LOONGARCH64)
>>       mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464");
>> +#elif defined(TARGET_LOONGARCH32)
>> +    mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("max32");
>
> Why can't we use it on LOONGARCH64?

I think many users are launching qemu-system-loongarch64 with default CPU,
better not to break them, so we only do max32 as default for
qemu-system-loongarch32.

Thanks
>
>> +#endif
>>       mc->default_ram_id = "loongarch.ram";
>>       mc->desc = "QEMU LoongArch Virtual Machine";
>>       mc->max_cpus = LOONGARCH_MAX_CPUS;
>>

-- 
- Jiaxun

Re: [PATCH v2 20/23] hw/loongarch/virt: Default to max32 CPU for LoongArch 32 build

[Philippe Mathieu-Daudé]

On 27/12/24 00:03, Jiaxun Yang wrote:
> 在2024年12月26日十二月 下午10:56，Philippe Mathieu-Daudé写道：
>> On 26/12/24 22:19, Jiaxun Yang wrote:
>>> la464 CPU is not available on LoongArch32. Use max32 which makes
>>> more sense here.
>>>
>>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>>> ---
>>>    hw/loongarch/virt.c | 4 ++++
>>>    1 file changed, 4 insertions(+)
>>>
>>> diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
>>> index 3a905cf71d46e3c5a29672f7bb73faedf1d29444..343d2e745e155d59f0ff17124b3c77ec9b3c111e 100644
>>> --- a/hw/loongarch/virt.c
>>> +++ b/hw/loongarch/virt.c
>>> @@ -1440,7 +1440,11 @@ static void virt_class_init(ObjectClass *oc, void *data)
>>>        HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
>>>    
>>>        mc->init = virt_init;
>>> +#if defined(TARGET_LOONGARCH64)
>>>        mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464");
>>> +#elif defined(TARGET_LOONGARCH32)
>>> +    mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("max32");
>>
>> Why can't we use it on LOONGARCH64?
> 
> I think many users are launching qemu-system-loongarch64 with default CPU,
> better not to break them, so we only do max32 as default for
> qemu-system-loongarch32.

Don't start with a default cpu on loongarch32! The user will get the
"no default cpu, use -cpu help to display them" and select max32 or any 
other :)

Re: [PATCH v2 23/23] config: Add loongarch32-softmmu target

[Richard Henderson]

On 12/26/24 14:58, Philippe Mathieu-Daudé wrote:
> On 26/12/24 22:19, Jiaxun Yang wrote:
>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> ---
>>   MAINTAINERS                                     | 4 ++--
>>   configs/devices/loongarch32-softmmu/default.mak | 7 +++++++
>>   configs/targets/loongarch32-softmmu.mak         | 7 +++++++
>>   3 files changed, 16 insertions(+), 2 deletions(-)
> 
> 
>> diff --git a/configs/targets/loongarch32-softmmu.mak b/configs/targets/loongarch32- 
>> softmmu.mak
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..50e0075a24ac6bf3717db967b03b816b52a25964
>> --- /dev/null
>> +++ b/configs/targets/loongarch32-softmmu.mak
>> @@ -0,0 +1,7 @@
>> +TARGET_ARCH=loongarch32
>> +TARGET_BASE_ARCH=loongarch
>> +TARGET_KVM_HAVE_GUEST_DEBUG=y
>> +TARGET_SUPPORTS_MTTCG=y
>> +TARGET_XML_FILES= gdb-xml/loongarch-base32.xml gdb-xml/loongarch-fpu.xml gdb-xml/ 
>> loongarch-lsx.xml gdb-xml/loongarch-lasx.xml
>> +# all boards require libfdt
>> +TARGET_NEED_FDT=y
>>
> 
> I'd really like, if possible, to not add a new target, but make the
> current loongarch64-softmmu.mak evolve to support both 32/64 modes.

Yes indeed.  I had assumed the preceding 32-bit target_ulong enablement was for linux-user.


r~

Re: [PATCH v2 23/23] config: Add loongarch32-softmmu target

[Jiaxun Yang]

在2024年12月27日十二月 上午5:20，Richard Henderson写道：
[...]
>>> +++ b/configs/targets/loongarch32-softmmu.mak
>>> @@ -0,0 +1,7 @@
>>> +TARGET_ARCH=loongarch32
>>> +TARGET_BASE_ARCH=loongarch
>>> +TARGET_KVM_HAVE_GUEST_DEBUG=y
>>> +TARGET_SUPPORTS_MTTCG=y
>>> +TARGET_XML_FILES= gdb-xml/loongarch-base32.xml gdb-xml/loongarch-fpu.xml gdb-xml/ 
>>> loongarch-lsx.xml gdb-xml/loongarch-lasx.xml
>>> +# all boards require libfdt
>>> +TARGET_NEED_FDT=y
>>>
>> 
>> I'd really like, if possible, to not add a new target, but make the
>> current loongarch64-softmmu.mak evolve to support both 32/64 modes.
>
> Yes indeed.  I had assumed the preceding 32-bit target_ulong enablement 
> was for linux-user.

Ok, I'll drop loongarch32-softmmu.mak for now.

It's indeed mostly for linux-user. I enabled softmmu just for validating the code.

Thanks
>
>
> r~

-- 
- Jiaxun

Re: [PATCH v2 21/23] qapi/machine: Replace TARGET_LOONGARCH64 with TARGET_LOONGARCH

[Markus Armbruster]

Jiaxun Yang <jiaxun.yang@flygoat.com> writes:

> All TARGET_LOONGARCH64 qapis are also available for LoongArch32 as we
> are reusing the same CPU backend implemenation.

As far as I can tell this makes query-cpu-model-expansion and
query-cpu-definitions in the LoongArch32 build, too.

> Use TARGET_LOONGARCH to identify LoongArch.

Suggest to be more explicit. e.g. like this:

  The QAPI commands specific to target loongarch64 are wanted for
  loongarch32, too.  These are query-cpu-model-expansion and
  query-cpu-definitions.  They just work, since the two use the same CPU
  implementation.

  Replace TARGET_LOONGARCH64 by TARGET_LOONGARCH.

> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

Preferably with an improved commit message
Acked-by: Markus Armbruster <armbru@redhat.com>