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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a457584bcsm2960097f8f.89.2024.12.26.15.02.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 26 Dec 2024 15:02:38 -0800 (PST) Message-ID: <3760c644-c5d4-4331-9d1b-059486bbd740@linaro.org> Date: Fri, 27 Dec 2024 00:02:36 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 06/23] target/loongarch: Store some uint64_t values as target_ulong To: Jiaxun Yang , QEMU devel Cc: Song Gao , Bibo Mao , Eric Blake , Markus Armbruster , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Zhao Liu , Paolo Bonzini References: <20241226-la32-fixes1-v2-0-0414594f8cb5@flygoat.com> <20241226-la32-fixes1-v2-6-0414594f8cb5@flygoat.com> <1f72e77a-5da9-4119-8e92-a707552f856f@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 26/12/24 23:58, Jiaxun Yang wrote: > > > 在2024年12月26日十二月 下午10:48，Philippe Mathieu-Daudé写道： >> On 26/12/24 22:19, Jiaxun Yang wrote: >>> Store internal registers including GPRs, CSRs, and LBT scratchs >>> as target_ulong, as per architecture specification. >>> >>> The only exception here is tlb_misc, as it's only used by QEMU >>> internally and need keep to be 64bit to store all required fields. >>> >>> There is no migration ABI change, as target_ulong is uint64_t on >>> existing loongarch64 builds anyway. >> >> I'm working on a prototype series where target_ulong becomes uint64_t >> under TCG. This patch is going the opposite direction. Not sure what >> to say at this point (I'm not rejecting it, just wondering). > > Does this mean TCGv will always be 64bit? > > I'm doing this just to keep all TCG _tl load/store sane. If that's the > way to go, I'm happy to adopt full uint64_t approach. "full uint64_t approach" won't happen before months (except if we get more manpower). The idea is to add all current generic TCG ops but taking an extra MemOp argument, having the backend sign-extending / truncating.