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Tue, 21 May 2024 16:37:51 +0000 (GMT) Received: from smtpav05.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5BF9358043; Tue, 21 May 2024 16:37:51 +0000 (GMT) Received: from mamboa4.aus.stglabs.ibm.com (unknown [9.3.84.87]) by smtpav05.wdc07v.mail.ibm.com (Postfix) with ESMTP; Tue, 21 May 2024 16:37:51 +0000 (GMT) Message-ID: <3794936cf8166557df9fd9f6fd440e77aaf9514d.camel@linux.ibm.com> Subject: Re: [PATCH v2 11/12] target/ppc: Implement SPRC/SPRD SPRs From: Miles Glenn To: Nicholas Piggin , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, Daniel Henrique Barboza , Richard Henderson , Chinmay Rath Date: Tue, 21 May 2024 11:37:51 -0500 In-Reply-To: <20240521013029.30082-12-npiggin@gmail.com> References: <20240521013029.30082-1-npiggin@gmail.com> <20240521013029.30082-12-npiggin@gmail.com> Organization: IBM Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-22.el8) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: tWaQlbRcGMKEh0on7B8wZJBNr_H2fzHC X-Proofpoint-ORIG-GUID: ioiR9I_Wjike7oXIuyzxBOVH8h7JTS4D X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-05-21_10,2024-05-21_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 mlxscore=0 priorityscore=1501 bulkscore=0 phishscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 spamscore=0 mlxlogscore=999 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405210126 Received-SPF: pass client-ip=148.163.156.1; envelope-from=milesg@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: milesg@linux.ibm.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reviewed-by: Glenn Miles Thanks, Glenn On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote: > This implements the POWER SPRC/SPRD SPRs, and SCRATCH0-7 registers > that > can be accessed via these indirect SPRs. > > SCRATCH registers only provide storage, but they are used by firmware > for low level crash and progress data, so this implementation logs > writes to the registers to help with analysis. > > Signed-off-by: Nicholas Piggin > --- > target/ppc/cpu.h | 7 +++-- > target/ppc/helper.h | 3 ++ > target/ppc/spr_common.h | 3 ++ > target/ppc/cpu_init.c | 10 ++++++ > target/ppc/misc_helper.c | 66 > ++++++++++++++++++++++++++++++++++++++++ > target/ppc/translate.c | 18 +++++++++++ > 6 files changed, 105 insertions(+), 2 deletions(-) > > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index 823be85d03..e4c342b17d 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -1264,6 +1264,9 @@ struct CPUArchState { > ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */ > struct CPUBreakpoint *ciabr_breakpoint; > struct CPUWatchpoint *dawr0_watchpoint; > + > + /* POWER CPU regs/state */ > + target_ulong scratch[8]; /* SCRATCH registers (shared across > core) */ > #endif > target_ulong sr[32]; /* segment registers */ > uint32_t nb_BATs; /* number of BATs */ > @@ -1806,9 +1809,9 @@ void ppc_compat_add_property(Object *obj, const > char *name, > #define SPR_SPRG2 (0x112) > #define SPR_SPRG3 (0x113) > #define SPR_SPRG4 (0x114) > -#define SPR_SCOMC (0x114) > +#define SPR_POWER_SPRC (0x114) > #define SPR_SPRG5 (0x115) > -#define SPR_SCOMD (0x115) > +#define SPR_POWER_SPRD (0x115) > #define SPR_SPRG6 (0x116) > #define SPR_SPRG7 (0x117) > #define SPR_ASR (0x118) > diff --git a/target/ppc/helper.h b/target/ppc/helper.h > index 09d50f9b76..57bf8354e7 100644 > --- a/target/ppc/helper.h > +++ b/target/ppc/helper.h > @@ -730,6 +730,9 @@ DEF_HELPER_2(book3s_msgsndp, void, env, tl) > DEF_HELPER_2(book3s_msgclrp, void, env, tl) > DEF_HELPER_1(load_tfmr, tl, env) > DEF_HELPER_2(store_tfmr, void, env, tl) > +DEF_HELPER_FLAGS_2(store_sprc, TCG_CALL_NO_RWG, void, env, tl) > +DEF_HELPER_FLAGS_1(load_sprd, TCG_CALL_NO_RWG_SE, tl, env) > +DEF_HELPER_FLAGS_2(store_sprd, TCG_CALL_NO_RWG, void, env, tl) > #endif > DEF_HELPER_2(store_sdr1, void, env, tl) > DEF_HELPER_2(store_pidr, void, env, tl) > diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h > index 85f73b860b..01aff449bc 100644 > --- a/target/ppc/spr_common.h > +++ b/target/ppc/spr_common.h > @@ -207,6 +207,9 @@ void spr_write_lpcr(DisasContext *ctx, int sprn, > int gprn); > void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn); > void spr_read_ppr32(DisasContext *ctx, int sprn, int gprn); > void spr_write_ppr32(DisasContext *ctx, int sprn, int gprn); > +void spr_write_sprc(DisasContext *ctx, int sprn, int gprn); > +void spr_read_sprd(DisasContext *ctx, int sprn, int gprn); > +void spr_write_sprd(DisasContext *ctx, int sprn, int gprn); > #endif > > void register_low_BATs(CPUPPCState *env); > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index 7f2f8e5a4a..f21dbcfefb 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -5794,6 +5794,16 @@ static void > register_power_common_book4_sprs(CPUPPCState *env) > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, &spr_core_write_generic, > 0x00000000); > + spr_register_hv(env, SPR_POWER_SPRC, "SPRC", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_sprc, > + 0x00000000); > + spr_register_hv(env, SPR_POWER_SPRD, "SPRD", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_sprd, &spr_write_sprd, > + 0x00000000); > #endif > } > > diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c > index a67930d031..fa47be2298 100644 > --- a/target/ppc/misc_helper.c > +++ b/target/ppc/misc_helper.c > @@ -307,6 +307,72 @@ void helper_store_dpdes(CPUPPCState *env, > target_ulong val) > } > bql_unlock(); > } > + > +/* Indirect SCOM (SPRC/SPRD) access to SCRATCH0-7 are implemented. > */ > +void helper_store_sprc(CPUPPCState *env, target_ulong val) > +{ > + if (val & ~0x3f8ULL) { > + qemu_log_mask(LOG_GUEST_ERROR, "Invalid SPRC register value > " > + TARGET_FMT_lx"\n", val); > + return; > + } > + env->spr[SPR_POWER_SPRC] = val; > +} > + > +target_ulong helper_load_sprd(CPUPPCState *env) > +{ > + target_ulong sprc = env->spr[SPR_POWER_SPRC]; > + > + switch (sprc & 0x3c0) { > + case 0: /* SCRATCH0-7 */ > + return env->scratch[(sprc >> 3) & 0x7]; > + default: > + qemu_log_mask(LOG_UNIMP, "mfSPRD: Unimplemented SPRC:0x" > + TARGET_FMT_lx"\n", sprc); > + break; > + } > + return 0; > +} > + > +static void do_store_scratch(CPUPPCState *env, int nr, target_ulong > val) > +{ > + CPUState *cs = env_cpu(env); > + CPUState *ccs; > + uint32_t nr_threads = cs->nr_threads; > + > + /* > + * Log stores to SCRATCH, because some firmware uses these for > debugging > + * and logging, but they would normally be read by the BMC, > which is > + * not implemented in QEMU yet. This gives a way to get at the > information. > + * Could also dump these upon checkstop. > + */ > + qemu_log("SPRD write 0x" TARGET_FMT_lx " to SCRATCH%d\n", val, > nr); > + > + if (nr_threads == 1) { > + env->scratch[nr] = val; > + return; > + } > + > + THREAD_SIBLING_FOREACH(cs, ccs) { > + CPUPPCState *cenv = &POWERPC_CPU(ccs)->env; > + cenv->scratch[nr] = val; > + } > +} > + > +void helper_store_sprd(CPUPPCState *env, target_ulong val) > +{ > + target_ulong sprc = env->spr[SPR_POWER_SPRC]; > + > + switch (sprc & 0x3c0) { > + case 0: /* SCRATCH0-7 */ > + do_store_scratch(env, (sprc >> 3) & 0x7, val); > + break; > + default: > + qemu_log_mask(LOG_UNIMP, "mfSPRD: Unimplemented SPRC:0x" > + TARGET_FMT_lx"\n", sprc); > + break; > + } > +} > #endif /* defined(TARGET_PPC64) */ > > void helper_store_pidr(CPUPPCState *env, target_ulong val) > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index 76f829ad12..ab11e48e3f 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -1363,6 +1363,24 @@ void spr_write_tfmr(DisasContext *ctx, int > sprn, int gprn) > gen_helper_store_tfmr(tcg_env, cpu_gpr[gprn]); > } > > +void spr_write_sprc(DisasContext *ctx, int sprn, int gprn) > +{ > + gen_helper_store_sprc(tcg_env, cpu_gpr[gprn]); > +} > + > +void spr_read_sprd(DisasContext *ctx, int gprn, int sprn) > +{ > + gen_helper_load_sprd(cpu_gpr[gprn], tcg_env); > +} > + > +void spr_write_sprd(DisasContext *ctx, int sprn, int gprn) > +{ > + if (!gen_serialize_core(ctx)) { > + return; > + } > + gen_helper_store_sprd(tcg_env, cpu_gpr[gprn]); > +} > + > void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) > { > translator_io_start(&ctx->base);