From: "Heiko Stübner" <heiko@sntech.de>
To: qemu-devel@nongnu.org
Cc: Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Atish Patra <atishp@rivosinc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
qemu-riscv@nongnu.org, Atish Patra <atishp@rivosinc.com>
Subject: Re: [PATCH] target/riscv: Add isa extenstion strings to the device tree
Date: Tue, 15 Feb 2022 10:58:37 +0100 [thread overview]
Message-ID: <3809640.nalusGk6Lh@diego> (raw)
In-Reply-To: <20220215090530.911828-1-atishp@rivosinc.com>
Hi Atish,
Am Dienstag, 15. Februar 2022, 10:05:30 CET schrieb Atish Patra:
> Append the available ISA extensions to the "riscv,isa" string if it
> is enabled so that kernel can process it.
For people glancing at these patches, a bit more insight into
how the isa string comes together might be helpful.
See question below for the reason ;-)
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
> target/riscv/cpu.c | 23 ++++++++++++++++++++++-
> 1 file changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index b0a40b83e7a8..c70260d0df15 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -34,6 +34,9 @@
>
> /* RISC-V CPU definitions */
>
> +/* This includes the null terminated character '\0' */
> +#define MAX_ISA_EXT_LEN 256
> +
> static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
>
> const char * const riscv_int_regnames[] = {
> @@ -881,10 +884,26 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
> device_class_set_props(dc, riscv_cpu_properties);
> }
>
> +static void riscv_isa_string_ext(RISCVCPU *cpu, char *isa_str, int max_str_len)
> +{
> + int offset = strnlen(isa_str, max_str_len);
> +
> + if (cpu->cfg.ext_svpbmt) {
> + offset += snprintf(isa_str + offset, max_str_len, "_%s", "_svpbmt");
is a double-"__" the correct divider for isa extensions?
I.e. you have "_%s" as well as "_svpbmt" here, which creates a double
underscore in the ISA string.
> + }
> + if ((offset < max_str_len) && cpu->cfg.ext_svinval) {
> + offset += snprintf(isa_str + offset, max_str_len, "_%s", "_svinval");
> + }
> + if ((offset < max_str_len) && (cpu->cfg.ext_svnapot)) {
> + offset += snprintf(isa_str + offset, max_str_len, "_%s", "_svnapot");
> + }
> +}
> +
> char *riscv_isa_string(RISCVCPU *cpu)
> {
> int i;
> - const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
> + const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) +
> + MAX_ISA_EXT_LEN;
> char *isa_str = g_new(char, maxlen);
> char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
> for (i = 0; i < sizeof(riscv_exts); i++) {
> @@ -893,6 +912,8 @@ char *riscv_isa_string(RISCVCPU *cpu)
> }
> }
> *p = '\0';
blank line here?
> + riscv_isa_string_ext(cpu, isa_str, maxlen);
> +
> return isa_str;
> }
Heiko
next prev parent reply other threads:[~2022-02-15 10:07 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-15 9:05 [PATCH] target/riscv: Add isa extenstion strings to the device tree Atish Patra
2022-02-15 9:58 ` Heiko Stübner [this message]
2022-02-15 16:20 ` Heiko Stübner
2022-02-15 19:39 ` Atish Patra
2022-02-15 21:20 ` Heiko Stübner
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