From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org,
qemu-s390x@nongnu.org, jcmvbkbc@gmail.com,
kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp,
gaosong@loongson.cn, jiaxun.yang@flygoat.com,
tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com,
edgar.iglesias@gmail.com
Subject: Re: [PATCH 56/70] target/tricore: Split t_n as constant from temp as variable
Date: Tue, 7 Mar 2023 01:19:11 +0100 [thread overview]
Message-ID: <38504dfd-e253-0efe-2188-b4b43a7bffe2@linaro.org> (raw)
In-Reply-To: <20230227054233.390271-57-richard.henderson@linaro.org>
On 27/2/23 06:42, Richard Henderson wrote:
> As required, allocate temp separately.
Hmm not quite accurate; this patch contains functions
which don't require separate temp and belong to the
next "All remaining uses are strictly read-only."
patch.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/tricore/translate.c | 268 +++++++++++++++++++------------------
> 1 file changed, 140 insertions(+), 128 deletions(-)
> @@ -647,22 +649,22 @@ static inline void
> gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
> TCGv r3, uint32_t n, uint32_t mode)
> {
> - TCGv temp = tcg_const_i32(n);
> + TCGv t_n = tcg_constant_i32(n);
"strictly read-only"
> TCGv_i64 temp64 = tcg_temp_new_i64();
> TCGv_i64 temp64_2 = tcg_temp_new_i64();
> TCGv_i64 temp64_3 = tcg_temp_new_i64();
> switch (mode) {
> case MODE_LL:
> - GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
> break;
> case MODE_LU:
> - GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
> break;
> case MODE_UL:
> - GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
> break;
> case MODE_UU:
> - GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
> break;
> }
> tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high);
> @@ -752,22 +756,22 @@ static inline void
> gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
> TCGv r3, uint32_t n, uint32_t mode)
> {
> - TCGv temp = tcg_const_i32(n);
> + TCGv t_n = tcg_constant_i32(n);
Ditto,
> TCGv_i64 temp64 = tcg_temp_new_i64();
> TCGv_i64 temp64_2 = tcg_temp_new_i64();
>
> switch (mode) {
> case MODE_LL:
> - GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
> break;
> case MODE_LU:
> - GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
> break;
> case MODE_UL:
> - GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
> break;
> case MODE_UU:
> - GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
> break;
> }
> tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
> @@ -785,22 +789,22 @@ static inline void
> gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
> TCGv r3, uint32_t n, uint32_t mode)
> {
> - TCGv temp = tcg_const_i32(n);
> + TCGv t_n = tcg_constant_i32(n);
etc...
> TCGv_i64 temp64 = tcg_temp_new_i64();
> TCGv_i64 temp64_2 = tcg_temp_new_i64();
> TCGv_i64 temp64_3 = tcg_temp_new_i64();
> switch (mode) {
> case MODE_LL:
> - GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
> + GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n);
> break;
> case MODE_LU:
> - GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
> + GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n);
> break;
> case MODE_UL:
> - GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
> + GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n);
> break;
> case MODE_UU:
> - GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
> + GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n);
> break;
> }
> tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
> @@ -813,21 +817,21 @@ static inline void
> gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
> TCGv r3, uint32_t n, uint32_t mode)
> {
> - TCGv temp = tcg_const_i32(n);
> + TCGv t_n = tcg_constant_i32(n);
> TCGv_i64 temp64 = tcg_temp_new_i64();
> TCGv_i64 temp64_2 = tcg_temp_new_i64();
> switch (mode) {
> case MODE_LL:
> - GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
> + GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n);
> break;
> case MODE_LU:
> - GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
> + GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n);
> break;
> case MODE_UL:
> - GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
> + GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n);
> break;
> case MODE_UU:
> - GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
> + GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n);
> break;
> }
> tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
> @@ -839,20 +843,20 @@ static inline void
> gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
> uint32_t mode)
> {
> - TCGv temp = tcg_const_i32(n);
> + TCGv t_n = tcg_constant_i32(n);
> TCGv_i64 temp64 = tcg_temp_new_i64();
> switch (mode) {
> case MODE_LL:
> - GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
> break;
> case MODE_LU:
> - GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
> break;
> case MODE_UL:
> - GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
> break;
> case MODE_UU:
> - GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
> break;
> }
> gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high);
> @@ -872,21 +876,22 @@ gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
> @@ -899,20 +904,20 @@ static inline void
> gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
> uint32_t n, uint32_t mode)
> {
> - TCGv temp = tcg_const_i32(n);
> + TCGv t_n = tcg_constant_i32(n);
> TCGv_i64 temp64 = tcg_temp_new_i64();
> switch (mode) {
> case MODE_LL:
> - GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
> break;
> case MODE_LU:
> - GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
> break;
> case MODE_UL:
> - GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
> break;
> case MODE_UU:
> - GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
> break;
> }
> gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
> @@ -1604,21 +1612,21 @@ static inline void
> gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
> TCGv r3, uint32_t n, uint32_t mode)
> {
> - TCGv temp = tcg_const_i32(n);
> + TCGv t_n = tcg_constant_i32(n);
> TCGv_i64 temp64 = tcg_temp_new_i64();
> TCGv_i64 temp64_2 = tcg_temp_new_i64();
> switch (mode) {
> case MODE_LL:
> - GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
> + GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n);
> break;
> case MODE_LU:
> - GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
> + GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n);
> break;
> case MODE_UL:
> - GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
> + GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n);
> break;
> case MODE_UU:
> - GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
> + GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n);
> break;
> }
> tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
> @@ -1630,20 +1638,20 @@ static inline void
> gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
> uint32_t mode)
> {
> - TCGv temp = tcg_const_i32(n);
> + TCGv t_n = tcg_constant_i32(n);
> TCGv_i64 temp64 = tcg_temp_new_i64();
> switch (mode) {
> case MODE_LL:
> - GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
> break;
> case MODE_LU:
> - GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
> break;
> case MODE_UL:
> - GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
> break;
> case MODE_UU:
> - GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
> break;
> }
> gen_helper_subr_h(ret, cpu_env, temp64, r1_low, r1_high);
> @@ -1664,20 +1672,20 @@ static inline void
> gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
> uint32_t n, uint32_t mode)
> {
> - TCGv temp = tcg_const_i32(n);
> + TCGv t_n = tcg_constant_i32(n);
> TCGv_i64 temp64 = tcg_temp_new_i64();
> switch (mode) {
> case MODE_LL:
> - GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
> break;
> case MODE_LU:
> - GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
> break;
> case MODE_UL:
> - GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
> break;
> case MODE_UU:
> - GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
> break;
> }
> gen_helper_subr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
> @@ -1912,10 +1920,10 @@ gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
> TCGv arg3, uint32_t n)
> {
> TCGv_i64 r1 = tcg_temp_new_i64();
> - TCGv temp = tcg_const_i32(n);
> + TCGv t_n = tcg_constant_i32(n);
>
> tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
> - gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp);
> + gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, t_n);
> tcg_gen_extr_i64_i32(rl, rh, r1);
> }
>
> @@ -1949,22 +1958,22 @@ static inline void
> gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
> TCGv r3, uint32_t n, uint32_t mode)
> {
> - TCGv temp = tcg_const_i32(n);
> + TCGv t_n = tcg_constant_i32(n);
> TCGv_i64 temp64 = tcg_temp_new_i64();
> TCGv_i64 temp64_2 = tcg_temp_new_i64();
> TCGv_i64 temp64_3 = tcg_temp_new_i64();
> switch (mode) {
> case MODE_LL:
> - GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
> break;
> case MODE_LU:
> - GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
> break;
> case MODE_UL:
> - GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
> break;
> case MODE_UU:
> - GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
> break;
> }
> tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high);
> @@ -2041,22 +2052,22 @@ static inline void
> gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
> TCGv r3, uint32_t n, uint32_t mode)
> {
> - TCGv temp = tcg_const_i32(n);
> + TCGv t_n = tcg_constant_i32(n);
> TCGv_i64 temp64 = tcg_temp_new_i64();
> TCGv_i64 temp64_2 = tcg_temp_new_i64();
>
> switch (mode) {
> case MODE_LL:
> - GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
> break;
> case MODE_LU:
> - GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
> break;
> case MODE_UL:
> - GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
> break;
> case MODE_UU:
> - GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
> + GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
> break;
> }
> tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
Regardless you split this patch, move parts to the
next patch, or keep as-is:
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
next prev parent reply other threads:[~2023-03-07 0:19 UTC|newest]
Thread overview: 140+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-27 5:41 [PATCH 00/70] tcg: Remove tcg_const_* Richard Henderson
2023-02-27 5:41 ` [PATCH 01/70] target/arm: Use rmode >= 0 for need_rmode Richard Henderson
2023-03-06 13:54 ` Philippe Mathieu-Daudé
2023-03-06 13:56 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 02/70] target/arm: Handle FPROUNDING_ODD in arm_rmode_to_sf Richard Henderson
2023-02-27 5:41 ` [PATCH 03/70] target/arm: Improve arm_rmode_to_sf Richard Henderson
2023-03-06 14:00 ` Philippe Mathieu-Daudé
2023-03-06 19:20 ` Richard Henderson
2023-02-27 5:41 ` [PATCH 04/70] target/arm: Consistently use ARMFPRounding during translation Richard Henderson
2023-03-06 13:58 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 05/70] target/arm: Create gen_set_rmode, gen_restore_rmode Richard Henderson
2023-02-27 5:41 ` [PATCH 06/70] target/arm: Improve trans_BFCI Richard Henderson
2023-02-27 5:41 ` [PATCH 07/70] target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str} Richard Henderson
2023-03-06 15:11 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 08/70] target/arm: Avoid tcg_const_* in translate-mve.c Richard Henderson
2023-02-27 5:41 ` [PATCH 09/70] target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn Richard Henderson
2023-02-27 5:41 ` [PATCH 10/70] target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn Richard Henderson
2023-03-06 15:15 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 11/70] target/arm: Avoid tcg_const_ptr in handle_rev Richard Henderson
2023-03-06 15:22 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 12/70] target/avr: Avoid use of tcg_const_i32 in SBIC, SBIS Richard Henderson
2023-03-06 13:51 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 13/70] target/avr: Avoid use of tcg_const_i32 throughout Richard Henderson
2023-03-06 23:49 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 14/70] target/cris: " Richard Henderson
2023-03-07 0:30 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 15/70] target/hexagon: Use tcg_constant_* for gen_constant_from_imm Richard Henderson
2023-02-27 21:55 ` Taylor Simpson
2023-02-27 5:41 ` [PATCH 16/70] target/hexagon/idef-parser: Use gen_tmp for LPCFG Richard Henderson
2023-02-27 21:55 ` Taylor Simpson
2023-02-27 5:41 ` [PATCH 17/70] target/hexagon/idef-parser: Use gen_tmp for gen_pred_assign Richard Henderson
2023-02-27 21:55 ` Taylor Simpson
2023-02-27 5:41 ` [PATCH 18/70] target/hexagon/idef-parser: Use gen_tmp for gen_rvalue_pred Richard Henderson
2023-02-27 21:55 ` Taylor Simpson
2023-02-27 5:41 ` [PATCH 19/70] target/hexagon/idef-parser: Use gen_constant for gen_extend_tcg_width_op Richard Henderson
2023-02-27 21:55 ` Taylor Simpson
2023-02-27 22:00 ` Richard Henderson
2023-02-27 22:38 ` Taylor Simpson
2023-02-27 5:41 ` [PATCH 20/70] target/hppa: Avoid tcg_const_i64 in trans_fid_f Richard Henderson
2023-03-06 13:50 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 21/70] target/hppa: Avoid use of tcg_const_i32 throughout Richard Henderson
2023-03-06 23:51 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 22/70] target/i386: Simplify POPF Richard Henderson
2023-02-27 9:04 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 23/70] target/i386: Avoid use of tcg_const_* throughout Richard Henderson
2023-03-07 0:37 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 24/70] target/m68k: Reject immediate as destination in gen_ea_mode Richard Henderson
2023-02-27 5:41 ` [PATCH 25/70] target/m68k: Use tcg_constant_i32 " Richard Henderson
2023-03-06 14:14 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 26/70] target/m68k: Avoid tcg_const_i32 when modified Richard Henderson
2023-03-06 23:53 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 27/70] target/m68k: Avoid tcg_const_i32 in bfop_reg Richard Henderson
2023-03-07 0:03 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 28/70] target/m68k: Avoid tcg_const_* throughout Richard Henderson
2023-03-06 23:59 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 29/70] target/microblaze: " Richard Henderson
2023-02-27 8:56 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 30/70] target/mips: Split out gen_lxl Richard Henderson
2023-03-06 13:31 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 31/70] target/mips: Split out gen_lxr Richard Henderson
2023-03-06 13:40 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 32/70] target/mips: Avoid tcg_const_tl in gen_r6_ld Richard Henderson
2023-03-06 13:41 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 33/70] target/mips: Avoid tcg_const_* throughout Richard Henderson
2023-03-06 13:46 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 34/70] target/ppc: Split out gen_vx_vmul10 Richard Henderson
2023-03-06 15:08 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 35/70] target/ppc: Avoid tcg_const_i64 in do_vector_shift_quad Richard Henderson
2023-03-06 14:16 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 36/70] target/ppc: Avoid tcg_const_i64 in do_vcntmb Richard Henderson
2023-02-27 5:42 ` [PATCH 37/70] target/ppc: Avoid tcg_const_* in vmx-impl.c.inc Richard Henderson
2023-02-27 5:42 ` [PATCH 38/70] target/ppc: Avoid tcg_const_* in xxeval Richard Henderson
2023-02-27 5:42 ` [PATCH 39/70] target/ppc: Avoid tcg_const_* in vsx-impl.c.inc Richard Henderson
2023-02-27 5:42 ` [PATCH 40/70] target/ppc: Avoid tcg_const_* in fp-impl.c.inc Richard Henderson
2023-02-27 5:42 ` [PATCH 41/70] target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc Richard Henderson
2023-02-27 5:42 ` [PATCH 42/70] target/ppc: Rewrite trans_ADDG6S Richard Henderson
2023-02-27 5:42 ` [PATCH 43/70] target/ppc: Fix gen_tlbsx_booke206 Richard Henderson
2023-02-27 5:42 ` [PATCH 44/70] target/ppc: Avoid tcg_const_* in translate.c Richard Henderson
2023-02-27 5:42 ` [PATCH 45/70] target/riscv: Avoid tcg_const_* Richard Henderson
2023-02-27 9:05 ` Philippe Mathieu-Daudé
2023-03-06 13:53 ` liweiwei
2023-02-27 5:42 ` [PATCH 46/70] target/rx: Use tcg_gen_abs_i32 Richard Henderson
2023-03-06 13:48 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 47/70] target/rx: Use cpu_psw_z as temp in flags computation Richard Henderson
2023-03-07 0:32 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 48/70] target/rx: Avoid tcg_const_i32 when new temp needed Richard Henderson
2023-03-06 14:18 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 49/70] target/rx: Avoid tcg_const_i32 Richard Henderson
2023-03-07 0:27 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 50/70] target/s390x: Split out gen_ri2 Richard Henderson
2023-02-27 9:09 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 51/70] target/s390x: Avoid tcg_const_i64 Richard Henderson
2023-03-07 0:21 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 52/70] target/sh4: Avoid tcg_const_i32 for TAS.B Richard Henderson
2023-03-07 0:23 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 53/70] target/sh4: Avoid tcg_const_i32 Richard Henderson
2023-03-07 0:21 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 54/70] tcg/sparc: Avoid tcg_const_tl in gen_edge Richard Henderson
2023-03-06 15:36 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 55/70] target/sparc: Avoid tcg_const_{tl,i32} Richard Henderson
2023-03-01 17:02 ` Mark Cave-Ayland
2023-03-06 15:37 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 56/70] target/tricore: Split t_n as constant from temp as variable Richard Henderson
2023-03-07 0:19 ` Philippe Mathieu-Daudé [this message]
2023-03-07 2:24 ` Richard Henderson
2023-03-07 10:20 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 57/70] target/tricore: Rename t_off10 and use tcg_constant_i32 Richard Henderson
2023-03-06 15:38 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 58/70] target/tricore: Use min/max for saturate Richard Henderson
2023-02-27 5:53 ` Richard Henderson
2023-02-27 5:42 ` [PATCH 59/70] target/tricore: Use setcondi instead of explicit allocation Richard Henderson
2023-03-06 15:39 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 60/70] target/tricore: Drop some temp initialization Richard Henderson
2023-03-06 15:25 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 61/70] target/tricore: Avoid tcg_const_i32 Richard Henderson
2023-03-07 0:10 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 62/70] target/xtensa: Tidy translate_bb Richard Henderson
2023-02-27 9:19 ` Max Filippov
2023-03-07 0:07 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 63/70] target/xtensa: Tidy translate_clamps Richard Henderson
2023-02-27 9:22 ` Max Filippov
2023-03-07 0:24 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 64/70] target/xtensa: Avoid tcg_const_i32 in translate_l32r Richard Henderson
2023-02-27 9:23 ` Max Filippov
2023-03-06 15:01 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 65/70] target/xtensa: Use tcg_gen_subfi_i32 in translate_sll Richard Henderson
2023-02-27 9:26 ` Max Filippov
2023-03-06 15:01 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 66/70] target/xtensa: Split constant in bit shift Richard Henderson
2023-02-27 9:27 ` Max Filippov
2023-03-06 15:01 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 67/70] target/xtensa: Avoid tcg_const_i32 Richard Henderson
2023-02-27 9:31 ` Max Filippov
2023-03-07 0:06 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 68/70] tcg: Replace tcg_const_i64 in tcg-op.c Richard Henderson
2023-03-06 15:33 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 69/70] tcg: Drop tcg_const_*_vec Richard Henderson
2023-03-06 15:32 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 70/70] tcg: Drop tcg_const_* Richard Henderson
2023-03-06 15:30 ` Philippe Mathieu-Daudé
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