* [Qemu-devel] [PATCH v1 1/5] RISC-V: Allow setting and clearing multiple irqs
2018-10-08 18:25 [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches Alistair Francis
@ 2018-10-08 18:25 ` Alistair Francis
2018-10-10 20:03 ` Palmer Dabbelt
2018-10-08 18:25 ` [Qemu-devel] [PATCH v1 2/5] RISC-V: Move non-ops from op_helper to cpu_helper Alistair Francis
` (4 subsequent siblings)
5 siblings, 1 reply; 25+ messages in thread
From: Alistair Francis @ 2018-10-08 18:25 UTC (permalink / raw)
To: qemu-devel@nongnu.org, mjc@sifive.com
Cc: Alistair Francis, alistair23@gmail.com
From: Michael Clark <mjc@sifive.com>
Change the API of riscv_set_local_interrupt to take a
write mask and value to allow setting and clearing of
multiple local interrupts atomically in a single call.
Rename the new function to riscv_cpu_update_mip.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_clint.c | 8 ++++----
hw/riscv/sifive_plic.c | 4 ++--
target/riscv/cpu.h | 22 +++++++++++++---------
target/riscv/op_helper.c | 24 +++++++++++++++---------
4 files changed, 34 insertions(+), 24 deletions(-)
diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c
index 7cc606e065..0d2fd52487 100644
--- a/hw/riscv/sifive_clint.c
+++ b/hw/riscv/sifive_clint.c
@@ -47,12 +47,12 @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value)
if (cpu->env.timecmp <= rtc_r) {
/* if we're setting an MTIMECMP value in the "past",
immediately raise the timer interrupt */
- riscv_set_local_interrupt(cpu, MIP_MTIP, 1);
+ riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));
return;
}
/* otherwise, set up the future timer interrupt */
- riscv_set_local_interrupt(cpu, MIP_MTIP, 0);
+ riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(0));
diff = cpu->env.timecmp - rtc_r;
/* back to ns (note args switched in muldiv64) */
next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
@@ -67,7 +67,7 @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value)
static void sifive_clint_timer_cb(void *opaque)
{
RISCVCPU *cpu = opaque;
- riscv_set_local_interrupt(cpu, MIP_MTIP, 1);
+ riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));
}
/* CPU wants to read rtc or timecmp register */
@@ -132,7 +132,7 @@ static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value,
if (!env) {
error_report("clint: invalid timecmp hartid: %zu", hartid);
} else if ((addr & 0x3) == 0) {
- riscv_set_local_interrupt(RISCV_CPU(cpu), MIP_MSIP, value != 0);
+ riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MSIP, BOOL_TO_MASK(value));
} else {
error_report("clint: invalid sip write: %08x", (uint32_t)addr);
}
diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index f635e6ff67..9cf9a1f986 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -142,10 +142,10 @@ static void sifive_plic_update(SiFivePLICState *plic)
int level = sifive_plic_irqs_pending(plic, addrid);
switch (mode) {
case PLICMode_M:
- riscv_set_local_interrupt(RISCV_CPU(cpu), MIP_MEIP, level);
+ riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level));
break;
case PLICMode_S:
- riscv_set_local_interrupt(RISCV_CPU(cpu), MIP_SEIP, level);
+ riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level));
break;
default:
break;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d4f36295f0..4ee09b9cff 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -126,13 +126,18 @@ struct CPURISCVState {
target_ulong mhartid;
target_ulong mstatus;
+
/*
* CAUTION! Unlike the rest of this struct, mip is accessed asynchonously
- * by I/O threads and other vCPUs, so hold the iothread mutex before
- * operating on it. CPU_INTERRUPT_HARD should be in effect iff this is
- * non-zero. Use riscv_cpu_set_local_interrupt.
+ * by I/O threads. It should be read with atomic_read. It should be updated
+ * using riscv_cpu_update_mip with the iothread mutex held. The iothread
+ * mutex must be held because mip must be consistent with the CPU inturrept
+ * state. riscv_cpu_update_mip calls cpu_interrupt or cpu_reset_interrupt
+ * wuth the invariant that CPU_INTERRUPT_HARD is set iff mip is non-zero.
+ * mip is 32-bits to allow atomic_read on 32-bit hosts.
*/
- uint32_t mip; /* allow atomic_read for >= 32-bit hosts */
+ uint32_t mip;
+
target_ulong mie;
target_ulong mideleg;
@@ -247,7 +252,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
uintptr_t retaddr);
int riscv_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size,
int rw, int mmu_idx);
-
char *riscv_isa_string(RISCVCPU *cpu);
void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
@@ -255,6 +259,10 @@ void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
#define cpu_list riscv_cpu_list
#define cpu_mmu_index riscv_cpu_mmu_index
+#ifndef CONFIG_USER_ONLY
+uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
+#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
+#endif
void riscv_set_mode(CPURISCVState *env, target_ulong newpriv);
void riscv_translate_init(void);
@@ -285,10 +293,6 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
target_ulong csrno);
target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno);
-#ifndef CONFIG_USER_ONLY
-void riscv_set_local_interrupt(RISCVCPU *cpu, target_ulong mask, int value);
-#endif
-
#include "exec/cpu-all.h"
#endif /* RISCV_CPU_H */
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index aec7558e1b..d0883d329b 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -171,10 +171,8 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
*/
qemu_mutex_lock_iothread();
RISCVCPU *cpu = riscv_env_get_cpu(env);
- riscv_set_local_interrupt(cpu, MIP_SSIP,
- (val_to_write & MIP_SSIP) != 0);
- riscv_set_local_interrupt(cpu, MIP_STIP,
- (val_to_write & MIP_STIP) != 0);
+ riscv_cpu_update_mip(cpu, MIP_SSIP | MIP_STIP,
+ (val_to_write & (MIP_SSIP | MIP_STIP)));
/*
* csrs, csrc on mip.SEIP is not decomposable into separate read and
* write steps, so a different implementation is needed
@@ -657,16 +655,24 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
#ifndef CONFIG_USER_ONLY
/* iothread_mutex must be held */
-void riscv_set_local_interrupt(RISCVCPU *cpu, target_ulong mask, int value)
+uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
{
- target_ulong old_mip = cpu->env.mip;
- cpu->env.mip = (old_mip & ~mask) | (value ? mask : 0);
+ CPURISCVState *env = &cpu->env;
+ uint32_t old, new, cmp = atomic_read(&env->mip);
- if (cpu->env.mip && !old_mip) {
+ do {
+ old = cmp;
+ new = (old & ~mask) | (value & mask);
+ cmp = atomic_cmpxchg(&env->mip, old, new);
+ } while (old != cmp);
+
+ if (new && !old) {
cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
- } else if (!cpu->env.mip && old_mip) {
+ } else if (!new && old) {
cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
}
+
+ return old;
}
void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)
--
2.17.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [Qemu-devel] [PATCH v1 1/5] RISC-V: Allow setting and clearing multiple irqs
2018-10-08 18:25 ` [Qemu-devel] [PATCH v1 1/5] RISC-V: Allow setting and clearing multiple irqs Alistair Francis
@ 2018-10-10 20:03 ` Palmer Dabbelt
0 siblings, 0 replies; 25+ messages in thread
From: Palmer Dabbelt @ 2018-10-10 20:03 UTC (permalink / raw)
Cc: qemu-devel, Michael Clark, alistair23, Alistair.Francis
On Mon, 08 Oct 2018 11:25:17 PDT (-0700), Alistair.Francis@wdc.com wrote:
> From: Michael Clark <mjc@sifive.com>
>
> Change the API of riscv_set_local_interrupt to take a
> write mask and value to allow setting and clearing of
> multiple local interrupts atomically in a single call.
> Rename the new function to riscv_cpu_update_mip.
>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/sifive_clint.c | 8 ++++----
> hw/riscv/sifive_plic.c | 4 ++--
> target/riscv/cpu.h | 22 +++++++++++++---------
> target/riscv/op_helper.c | 24 +++++++++++++++---------
> 4 files changed, 34 insertions(+), 24 deletions(-)
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
> diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c
> index 7cc606e065..0d2fd52487 100644
> --- a/hw/riscv/sifive_clint.c
> +++ b/hw/riscv/sifive_clint.c
> @@ -47,12 +47,12 @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value)
> if (cpu->env.timecmp <= rtc_r) {
> /* if we're setting an MTIMECMP value in the "past",
> immediately raise the timer interrupt */
> - riscv_set_local_interrupt(cpu, MIP_MTIP, 1);
> + riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));
> return;
> }
>
> /* otherwise, set up the future timer interrupt */
> - riscv_set_local_interrupt(cpu, MIP_MTIP, 0);
> + riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(0));
> diff = cpu->env.timecmp - rtc_r;
> /* back to ns (note args switched in muldiv64) */
> next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
> @@ -67,7 +67,7 @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value)
> static void sifive_clint_timer_cb(void *opaque)
> {
> RISCVCPU *cpu = opaque;
> - riscv_set_local_interrupt(cpu, MIP_MTIP, 1);
> + riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));
> }
>
> /* CPU wants to read rtc or timecmp register */
> @@ -132,7 +132,7 @@ static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value,
> if (!env) {
> error_report("clint: invalid timecmp hartid: %zu", hartid);
> } else if ((addr & 0x3) == 0) {
> - riscv_set_local_interrupt(RISCV_CPU(cpu), MIP_MSIP, value != 0);
> + riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MSIP, BOOL_TO_MASK(value));
> } else {
> error_report("clint: invalid sip write: %08x", (uint32_t)addr);
> }
> diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
> index f635e6ff67..9cf9a1f986 100644
> --- a/hw/riscv/sifive_plic.c
> +++ b/hw/riscv/sifive_plic.c
> @@ -142,10 +142,10 @@ static void sifive_plic_update(SiFivePLICState *plic)
> int level = sifive_plic_irqs_pending(plic, addrid);
> switch (mode) {
> case PLICMode_M:
> - riscv_set_local_interrupt(RISCV_CPU(cpu), MIP_MEIP, level);
> + riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level));
> break;
> case PLICMode_S:
> - riscv_set_local_interrupt(RISCV_CPU(cpu), MIP_SEIP, level);
> + riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level));
> break;
> default:
> break;
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index d4f36295f0..4ee09b9cff 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -126,13 +126,18 @@ struct CPURISCVState {
>
> target_ulong mhartid;
> target_ulong mstatus;
> +
> /*
> * CAUTION! Unlike the rest of this struct, mip is accessed asynchonously
> - * by I/O threads and other vCPUs, so hold the iothread mutex before
> - * operating on it. CPU_INTERRUPT_HARD should be in effect iff this is
> - * non-zero. Use riscv_cpu_set_local_interrupt.
> + * by I/O threads. It should be read with atomic_read. It should be updated
> + * using riscv_cpu_update_mip with the iothread mutex held. The iothread
> + * mutex must be held because mip must be consistent with the CPU inturrept
> + * state. riscv_cpu_update_mip calls cpu_interrupt or cpu_reset_interrupt
> + * wuth the invariant that CPU_INTERRUPT_HARD is set iff mip is non-zero.
> + * mip is 32-bits to allow atomic_read on 32-bit hosts.
> */
> - uint32_t mip; /* allow atomic_read for >= 32-bit hosts */
> + uint32_t mip;
> +
> target_ulong mie;
> target_ulong mideleg;
>
> @@ -247,7 +252,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> uintptr_t retaddr);
> int riscv_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size,
> int rw, int mmu_idx);
> -
> char *riscv_isa_string(RISCVCPU *cpu);
> void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
>
> @@ -255,6 +259,10 @@ void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
> #define cpu_list riscv_cpu_list
> #define cpu_mmu_index riscv_cpu_mmu_index
>
> +#ifndef CONFIG_USER_ONLY
> +uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
> +#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
> +#endif
> void riscv_set_mode(CPURISCVState *env, target_ulong newpriv);
>
> void riscv_translate_init(void);
> @@ -285,10 +293,6 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
> target_ulong csrno);
> target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno);
>
> -#ifndef CONFIG_USER_ONLY
> -void riscv_set_local_interrupt(RISCVCPU *cpu, target_ulong mask, int value);
> -#endif
> -
> #include "exec/cpu-all.h"
>
> #endif /* RISCV_CPU_H */
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index aec7558e1b..d0883d329b 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -171,10 +171,8 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
> */
> qemu_mutex_lock_iothread();
> RISCVCPU *cpu = riscv_env_get_cpu(env);
> - riscv_set_local_interrupt(cpu, MIP_SSIP,
> - (val_to_write & MIP_SSIP) != 0);
> - riscv_set_local_interrupt(cpu, MIP_STIP,
> - (val_to_write & MIP_STIP) != 0);
> + riscv_cpu_update_mip(cpu, MIP_SSIP | MIP_STIP,
> + (val_to_write & (MIP_SSIP | MIP_STIP)));
> /*
> * csrs, csrc on mip.SEIP is not decomposable into separate read and
> * write steps, so a different implementation is needed
> @@ -657,16 +655,24 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
> #ifndef CONFIG_USER_ONLY
>
> /* iothread_mutex must be held */
> -void riscv_set_local_interrupt(RISCVCPU *cpu, target_ulong mask, int value)
> +uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
> {
> - target_ulong old_mip = cpu->env.mip;
> - cpu->env.mip = (old_mip & ~mask) | (value ? mask : 0);
> + CPURISCVState *env = &cpu->env;
> + uint32_t old, new, cmp = atomic_read(&env->mip);
>
> - if (cpu->env.mip && !old_mip) {
> + do {
> + old = cmp;
> + new = (old & ~mask) | (value & mask);
> + cmp = atomic_cmpxchg(&env->mip, old, new);
> + } while (old != cmp);
> +
> + if (new && !old) {
> cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
> - } else if (!cpu->env.mip && old_mip) {
> + } else if (!new && old) {
> cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
> }
> +
> + return old;
> }
>
> void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)
> --
> 2.17.1
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v1 2/5] RISC-V: Move non-ops from op_helper to cpu_helper
2018-10-08 18:25 [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches Alistair Francis
2018-10-08 18:25 ` [Qemu-devel] [PATCH v1 1/5] RISC-V: Allow setting and clearing multiple irqs Alistair Francis
@ 2018-10-08 18:25 ` Alistair Francis
2018-10-10 19:07 ` Philippe Mathieu-Daudé
2018-10-10 20:03 ` Palmer Dabbelt
2018-10-08 18:25 ` [Qemu-devel] [PATCH v1 3/5] RISC-V: Update CSR and interrupt definitions Alistair Francis
` (3 subsequent siblings)
5 siblings, 2 replies; 25+ messages in thread
From: Alistair Francis @ 2018-10-08 18:25 UTC (permalink / raw)
To: qemu-devel@nongnu.org, mjc@sifive.com
Cc: Alistair Francis, alistair23@gmail.com
From: Michael Clark <mjc@sifive.com>
This patch makes op_helper.c contain only instruction
operation helpers used by translate.c and moves any
unrelated cpu helpers into cpu_helper.c. No logic is
changed by this patch.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/Makefile.objs | 2 +-
target/riscv/{helper.c => cpu_helper.c} | 35 ++++++++++++++++++++++++-
target/riscv/op_helper.c | 34 ------------------------
3 files changed, 35 insertions(+), 36 deletions(-)
rename target/riscv/{helper.c => cpu_helper.c} (95%)
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index abd0a7cde3..fcc5d34c1f 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -1 +1 @@
-obj-y += translate.o op_helper.o helper.o cpu.o fpu_helper.o gdbstub.o pmp.o
+obj-y += translate.o op_helper.o cpu_helper.o cpu.o fpu_helper.o gdbstub.o pmp.o
diff --git a/target/riscv/helper.c b/target/riscv/cpu_helper.c
similarity index 95%
rename from target/riscv/helper.c
rename to target/riscv/cpu_helper.c
index 63b3386b76..86f9f4730c 100644
--- a/target/riscv/helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1,5 +1,5 @@
/*
- * RISC-V emulation helpers for qemu.
+ * RISC-V CPU helpers for qemu.
*
* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
* Copyright (c) 2017-2018 SiFive, Inc.
@@ -72,6 +72,39 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
#if !defined(CONFIG_USER_ONLY)
+/* iothread_mutex must be held */
+uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
+{
+ CPURISCVState *env = &cpu->env;
+ uint32_t old, new, cmp = atomic_read(&env->mip);
+
+ do {
+ old = cmp;
+ new = (old & ~mask) | (value & mask);
+ cmp = atomic_cmpxchg(&env->mip, old, new);
+ } while (old != cmp);
+
+ if (new && !old) {
+ cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
+ } else if (!new && old) {
+ cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
+ }
+
+ return old;
+}
+
+void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)
+{
+ if (newpriv > PRV_M) {
+ g_assert_not_reached();
+ }
+ if (newpriv == PRV_H) {
+ newpriv = PRV_U;
+ }
+ /* tlb_flush is unnecessary as mode is contained in mmu_idx */
+ env->priv = newpriv;
+}
+
/* get_physical_address - get the physical address for this virtual address
*
* Do a page table walk to obtain the physical address corresponding to a
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index d0883d329b..495390ab1c 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -654,39 +654,6 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
#ifndef CONFIG_USER_ONLY
-/* iothread_mutex must be held */
-uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
-{
- CPURISCVState *env = &cpu->env;
- uint32_t old, new, cmp = atomic_read(&env->mip);
-
- do {
- old = cmp;
- new = (old & ~mask) | (value & mask);
- cmp = atomic_cmpxchg(&env->mip, old, new);
- } while (old != cmp);
-
- if (new && !old) {
- cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
- } else if (!new && old) {
- cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
- }
-
- return old;
-}
-
-void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)
-{
- if (newpriv > PRV_M) {
- g_assert_not_reached();
- }
- if (newpriv == PRV_H) {
- newpriv = PRV_U;
- }
- /* tlb_flush is unnecessary as mode is contained in mmu_idx */
- env->priv = newpriv;
-}
-
target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
{
if (!(env->priv >= PRV_S)) {
@@ -737,7 +704,6 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
return retpc;
}
-
void helper_wfi(CPURISCVState *env)
{
CPUState *cs = CPU(riscv_env_get_cpu(env));
--
2.17.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [Qemu-devel] [PATCH v1 2/5] RISC-V: Move non-ops from op_helper to cpu_helper
2018-10-08 18:25 ` [Qemu-devel] [PATCH v1 2/5] RISC-V: Move non-ops from op_helper to cpu_helper Alistair Francis
@ 2018-10-10 19:07 ` Philippe Mathieu-Daudé
2018-10-10 20:03 ` Palmer Dabbelt
1 sibling, 0 replies; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-10-10 19:07 UTC (permalink / raw)
To: Alistair Francis, qemu-devel@nongnu.org, mjc@sifive.com
Cc: alistair23@gmail.com
On 08/10/2018 20:25, Alistair Francis wrote:
> From: Michael Clark <mjc@sifive.com>
>
> This patch makes op_helper.c contain only instruction
> operation helpers used by translate.c and moves any
> unrelated cpu helpers into cpu_helper.c. No logic is
> changed by this patch.
>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> target/riscv/Makefile.objs | 2 +-
> target/riscv/{helper.c => cpu_helper.c} | 35 ++++++++++++++++++++++++-
> target/riscv/op_helper.c | 34 ------------------------
> 3 files changed, 35 insertions(+), 36 deletions(-)
> rename target/riscv/{helper.c => cpu_helper.c} (95%)
>
> diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
> index abd0a7cde3..fcc5d34c1f 100644
> --- a/target/riscv/Makefile.objs
> +++ b/target/riscv/Makefile.objs
> @@ -1 +1 @@
> -obj-y += translate.o op_helper.o helper.o cpu.o fpu_helper.o gdbstub.o pmp.o
> +obj-y += translate.o op_helper.o cpu_helper.o cpu.o fpu_helper.o gdbstub.o pmp.o
> diff --git a/target/riscv/helper.c b/target/riscv/cpu_helper.c
> similarity index 95%
> rename from target/riscv/helper.c
> rename to target/riscv/cpu_helper.c
> index 63b3386b76..86f9f4730c 100644
> --- a/target/riscv/helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -1,5 +1,5 @@
> /*
> - * RISC-V emulation helpers for qemu.
> + * RISC-V CPU helpers for qemu.
> *
> * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
> * Copyright (c) 2017-2018 SiFive, Inc.
> @@ -72,6 +72,39 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
>
> #if !defined(CONFIG_USER_ONLY)
>
> +/* iothread_mutex must be held */
> +uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
> +{
> + CPURISCVState *env = &cpu->env;
> + uint32_t old, new, cmp = atomic_read(&env->mip);
> +
> + do {
> + old = cmp;
> + new = (old & ~mask) | (value & mask);
> + cmp = atomic_cmpxchg(&env->mip, old, new);
> + } while (old != cmp);
> +
> + if (new && !old) {
> + cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
> + } else if (!new && old) {
> + cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
> + }
> +
> + return old;
> +}
> +
> +void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)
> +{
> + if (newpriv > PRV_M) {
> + g_assert_not_reached();
> + }
> + if (newpriv == PRV_H) {
> + newpriv = PRV_U;
> + }
> + /* tlb_flush is unnecessary as mode is contained in mmu_idx */
> + env->priv = newpriv;
> +}
> +
> /* get_physical_address - get the physical address for this virtual address
> *
> * Do a page table walk to obtain the physical address corresponding to a
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index d0883d329b..495390ab1c 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -654,39 +654,6 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
>
> #ifndef CONFIG_USER_ONLY
>
> -/* iothread_mutex must be held */
> -uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
> -{
> - CPURISCVState *env = &cpu->env;
> - uint32_t old, new, cmp = atomic_read(&env->mip);
> -
> - do {
> - old = cmp;
> - new = (old & ~mask) | (value & mask);
> - cmp = atomic_cmpxchg(&env->mip, old, new);
> - } while (old != cmp);
> -
> - if (new && !old) {
> - cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
> - } else if (!new && old) {
> - cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
> - }
> -
> - return old;
> -}
> -
> -void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)
> -{
> - if (newpriv > PRV_M) {
> - g_assert_not_reached();
> - }
> - if (newpriv == PRV_H) {
> - newpriv = PRV_U;
> - }
> - /* tlb_flush is unnecessary as mode is contained in mmu_idx */
> - env->priv = newpriv;
> -}
> -
> target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
> {
> if (!(env->priv >= PRV_S)) {
> @@ -737,7 +704,6 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
> return retpc;
> }
>
> -
> void helper_wfi(CPURISCVState *env)
> {
> CPUState *cs = CPU(riscv_env_get_cpu(env));
>
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [Qemu-devel] [PATCH v1 2/5] RISC-V: Move non-ops from op_helper to cpu_helper
2018-10-08 18:25 ` [Qemu-devel] [PATCH v1 2/5] RISC-V: Move non-ops from op_helper to cpu_helper Alistair Francis
2018-10-10 19:07 ` Philippe Mathieu-Daudé
@ 2018-10-10 20:03 ` Palmer Dabbelt
1 sibling, 0 replies; 25+ messages in thread
From: Palmer Dabbelt @ 2018-10-10 20:03 UTC (permalink / raw)
Cc: qemu-devel, Michael Clark, alistair23, Alistair.Francis
On Mon, 08 Oct 2018 11:25:27 PDT (-0700), Alistair.Francis@wdc.com wrote:
> From: Michael Clark <mjc@sifive.com>
>
> This patch makes op_helper.c contain only instruction
> operation helpers used by translate.c and moves any
> unrelated cpu helpers into cpu_helper.c. No logic is
> changed by this patch.
>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/Makefile.objs | 2 +-
> target/riscv/{helper.c => cpu_helper.c} | 35 ++++++++++++++++++++++++-
> target/riscv/op_helper.c | 34 ------------------------
> 3 files changed, 35 insertions(+), 36 deletions(-)
> rename target/riscv/{helper.c => cpu_helper.c} (95%)
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
> diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
> index abd0a7cde3..fcc5d34c1f 100644
> --- a/target/riscv/Makefile.objs
> +++ b/target/riscv/Makefile.objs
> @@ -1 +1 @@
> -obj-y += translate.o op_helper.o helper.o cpu.o fpu_helper.o gdbstub.o pmp.o
> +obj-y += translate.o op_helper.o cpu_helper.o cpu.o fpu_helper.o gdbstub.o pmp.o
> diff --git a/target/riscv/helper.c b/target/riscv/cpu_helper.c
> similarity index 95%
> rename from target/riscv/helper.c
> rename to target/riscv/cpu_helper.c
> index 63b3386b76..86f9f4730c 100644
> --- a/target/riscv/helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -1,5 +1,5 @@
> /*
> - * RISC-V emulation helpers for qemu.
> + * RISC-V CPU helpers for qemu.
> *
> * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
> * Copyright (c) 2017-2018 SiFive, Inc.
> @@ -72,6 +72,39 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
>
> #if !defined(CONFIG_USER_ONLY)
>
> +/* iothread_mutex must be held */
> +uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
> +{
> + CPURISCVState *env = &cpu->env;
> + uint32_t old, new, cmp = atomic_read(&env->mip);
> +
> + do {
> + old = cmp;
> + new = (old & ~mask) | (value & mask);
> + cmp = atomic_cmpxchg(&env->mip, old, new);
> + } while (old != cmp);
> +
> + if (new && !old) {
> + cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
> + } else if (!new && old) {
> + cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
> + }
> +
> + return old;
> +}
> +
> +void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)
> +{
> + if (newpriv > PRV_M) {
> + g_assert_not_reached();
> + }
> + if (newpriv == PRV_H) {
> + newpriv = PRV_U;
> + }
> + /* tlb_flush is unnecessary as mode is contained in mmu_idx */
> + env->priv = newpriv;
> +}
> +
> /* get_physical_address - get the physical address for this virtual address
> *
> * Do a page table walk to obtain the physical address corresponding to a
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index d0883d329b..495390ab1c 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -654,39 +654,6 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
>
> #ifndef CONFIG_USER_ONLY
>
> -/* iothread_mutex must be held */
> -uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
> -{
> - CPURISCVState *env = &cpu->env;
> - uint32_t old, new, cmp = atomic_read(&env->mip);
> -
> - do {
> - old = cmp;
> - new = (old & ~mask) | (value & mask);
> - cmp = atomic_cmpxchg(&env->mip, old, new);
> - } while (old != cmp);
> -
> - if (new && !old) {
> - cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
> - } else if (!new && old) {
> - cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
> - }
> -
> - return old;
> -}
> -
> -void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)
> -{
> - if (newpriv > PRV_M) {
> - g_assert_not_reached();
> - }
> - if (newpriv == PRV_H) {
> - newpriv = PRV_U;
> - }
> - /* tlb_flush is unnecessary as mode is contained in mmu_idx */
> - env->priv = newpriv;
> -}
> -
> target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
> {
> if (!(env->priv >= PRV_S)) {
> @@ -737,7 +704,6 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
> return retpc;
> }
>
> -
> void helper_wfi(CPURISCVState *env)
> {
> CPUState *cs = CPU(riscv_env_get_cpu(env));
> --
> 2.17.1
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v1 3/5] RISC-V: Update CSR and interrupt definitions
2018-10-08 18:25 [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches Alistair Francis
2018-10-08 18:25 ` [Qemu-devel] [PATCH v1 1/5] RISC-V: Allow setting and clearing multiple irqs Alistair Francis
2018-10-08 18:25 ` [Qemu-devel] [PATCH v1 2/5] RISC-V: Move non-ops from op_helper to cpu_helper Alistair Francis
@ 2018-10-08 18:25 ` Alistair Francis
2018-10-10 20:03 ` Palmer Dabbelt
2018-10-08 18:25 ` [Qemu-devel] [PATCH v1 4/5] RISC-V: Add missing free for plic_hart_config Alistair Francis
` (2 subsequent siblings)
5 siblings, 1 reply; 25+ messages in thread
From: Alistair Francis @ 2018-10-08 18:25 UTC (permalink / raw)
To: qemu-devel@nongnu.org, mjc@sifive.com
Cc: Alistair Francis, alistair23@gmail.com
From: Michael Clark <mjc@sifive.com>
* Add user-mode CSR defininitions.
* Reorder CSR definitions to match the specification.
* Change H mode interrupt comment to 'reserved'.
* Remove unused X_COP interrupt.
* Add user-mode interrupts.
* Remove erroneous until comments on machine mode interrupts.
* Move together paging mode and page table bit definitions.
* Move together interrupt and exception cause definitions.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 6 +-
target/riscv/cpu_bits.h | 683 +++++++++++++++++++++------------------
target/riscv/op_helper.c | 2 +-
3 files changed, 370 insertions(+), 321 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d630e8fd6c..a025a0a3ba 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -74,8 +74,10 @@ const char * const riscv_intr_names[] = {
"s_external",
"h_external",
"m_external",
- "coprocessor",
- "host"
+ "reserved",
+ "reserved",
+ "reserved",
+ "reserved"
};
typedef struct RISCVCPUInfo {
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 12b4757088..5439f4719e 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -6,242 +6,283 @@
(((target_ulong)(val) * ((mask) & ~((mask) << 1))) & \
(target_ulong)(mask)))
-#define PGSHIFT 12
-
-#define FSR_RD_SHIFT 5
-#define FSR_RD (0x7 << FSR_RD_SHIFT)
-
-#define FPEXC_NX 0x01
-#define FPEXC_UF 0x02
-#define FPEXC_OF 0x04
-#define FPEXC_DZ 0x08
-#define FPEXC_NV 0x10
-
-#define FSR_AEXC_SHIFT 0
-#define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT)
-#define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT)
-#define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT)
-#define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT)
-#define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
-#define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
-
-/* CSR numbers */
-#define CSR_FFLAGS 0x1
-#define CSR_FRM 0x2
-#define CSR_FCSR 0x3
-#define CSR_CYCLE 0xc00
-#define CSR_TIME 0xc01
-#define CSR_INSTRET 0xc02
-#define CSR_HPMCOUNTER3 0xc03
-#define CSR_HPMCOUNTER4 0xc04
-#define CSR_HPMCOUNTER5 0xc05
-#define CSR_HPMCOUNTER6 0xc06
-#define CSR_HPMCOUNTER7 0xc07
-#define CSR_HPMCOUNTER8 0xc08
-#define CSR_HPMCOUNTER9 0xc09
-#define CSR_HPMCOUNTER10 0xc0a
-#define CSR_HPMCOUNTER11 0xc0b
-#define CSR_HPMCOUNTER12 0xc0c
-#define CSR_HPMCOUNTER13 0xc0d
-#define CSR_HPMCOUNTER14 0xc0e
-#define CSR_HPMCOUNTER15 0xc0f
-#define CSR_HPMCOUNTER16 0xc10
-#define CSR_HPMCOUNTER17 0xc11
-#define CSR_HPMCOUNTER18 0xc12
-#define CSR_HPMCOUNTER19 0xc13
-#define CSR_HPMCOUNTER20 0xc14
-#define CSR_HPMCOUNTER21 0xc15
-#define CSR_HPMCOUNTER22 0xc16
-#define CSR_HPMCOUNTER23 0xc17
-#define CSR_HPMCOUNTER24 0xc18
-#define CSR_HPMCOUNTER25 0xc19
-#define CSR_HPMCOUNTER26 0xc1a
-#define CSR_HPMCOUNTER27 0xc1b
-#define CSR_HPMCOUNTER28 0xc1c
-#define CSR_HPMCOUNTER29 0xc1d
-#define CSR_HPMCOUNTER30 0xc1e
-#define CSR_HPMCOUNTER31 0xc1f
-#define CSR_SSTATUS 0x100
-#define CSR_SIE 0x104
-#define CSR_STVEC 0x105
-#define CSR_SCOUNTEREN 0x106
-#define CSR_SSCRATCH 0x140
-#define CSR_SEPC 0x141
-#define CSR_SCAUSE 0x142
-#define CSR_SBADADDR 0x143
-#define CSR_SIP 0x144
-#define CSR_SPTBR 0x180
-#define CSR_SATP 0x180
-#define CSR_MSTATUS 0x300
-#define CSR_MISA 0x301
-#define CSR_MEDELEG 0x302
-#define CSR_MIDELEG 0x303
-#define CSR_MIE 0x304
-#define CSR_MTVEC 0x305
-#define CSR_MCOUNTEREN 0x306
-#define CSR_MSCRATCH 0x340
-#define CSR_MEPC 0x341
-#define CSR_MCAUSE 0x342
-#define CSR_MBADADDR 0x343
-#define CSR_MIP 0x344
-#define CSR_PMPCFG0 0x3a0
-#define CSR_PMPCFG1 0x3a1
-#define CSR_PMPCFG2 0x3a2
-#define CSR_PMPCFG3 0x3a3
-#define CSR_PMPADDR0 0x3b0
-#define CSR_PMPADDR1 0x3b1
-#define CSR_PMPADDR2 0x3b2
-#define CSR_PMPADDR3 0x3b3
-#define CSR_PMPADDR4 0x3b4
-#define CSR_PMPADDR5 0x3b5
-#define CSR_PMPADDR6 0x3b6
-#define CSR_PMPADDR7 0x3b7
-#define CSR_PMPADDR8 0x3b8
-#define CSR_PMPADDR9 0x3b9
-#define CSR_PMPADDR10 0x3ba
-#define CSR_PMPADDR11 0x3bb
-#define CSR_PMPADDR12 0x3bc
-#define CSR_PMPADDR13 0x3bd
-#define CSR_PMPADDR14 0x3be
-#define CSR_PMPADDR15 0x3bf
-#define CSR_TSELECT 0x7a0
-#define CSR_TDATA1 0x7a1
-#define CSR_TDATA2 0x7a2
-#define CSR_TDATA3 0x7a3
-#define CSR_DCSR 0x7b0
-#define CSR_DPC 0x7b1
-#define CSR_DSCRATCH 0x7b2
-#define CSR_MCYCLE 0xb00
-#define CSR_MINSTRET 0xb02
-#define CSR_MHPMCOUNTER3 0xb03
-#define CSR_MHPMCOUNTER4 0xb04
-#define CSR_MHPMCOUNTER5 0xb05
-#define CSR_MHPMCOUNTER6 0xb06
-#define CSR_MHPMCOUNTER7 0xb07
-#define CSR_MHPMCOUNTER8 0xb08
-#define CSR_MHPMCOUNTER9 0xb09
-#define CSR_MHPMCOUNTER10 0xb0a
-#define CSR_MHPMCOUNTER11 0xb0b
-#define CSR_MHPMCOUNTER12 0xb0c
-#define CSR_MHPMCOUNTER13 0xb0d
-#define CSR_MHPMCOUNTER14 0xb0e
-#define CSR_MHPMCOUNTER15 0xb0f
-#define CSR_MHPMCOUNTER16 0xb10
-#define CSR_MHPMCOUNTER17 0xb11
-#define CSR_MHPMCOUNTER18 0xb12
-#define CSR_MHPMCOUNTER19 0xb13
-#define CSR_MHPMCOUNTER20 0xb14
-#define CSR_MHPMCOUNTER21 0xb15
-#define CSR_MHPMCOUNTER22 0xb16
-#define CSR_MHPMCOUNTER23 0xb17
-#define CSR_MHPMCOUNTER24 0xb18
-#define CSR_MHPMCOUNTER25 0xb19
-#define CSR_MHPMCOUNTER26 0xb1a
-#define CSR_MHPMCOUNTER27 0xb1b
-#define CSR_MHPMCOUNTER28 0xb1c
-#define CSR_MHPMCOUNTER29 0xb1d
-#define CSR_MHPMCOUNTER30 0xb1e
-#define CSR_MHPMCOUNTER31 0xb1f
-#define CSR_MUCOUNTEREN 0x320
-#define CSR_MSCOUNTEREN 0x321
-#define CSR_MHPMEVENT3 0x323
-#define CSR_MHPMEVENT4 0x324
-#define CSR_MHPMEVENT5 0x325
-#define CSR_MHPMEVENT6 0x326
-#define CSR_MHPMEVENT7 0x327
-#define CSR_MHPMEVENT8 0x328
-#define CSR_MHPMEVENT9 0x329
-#define CSR_MHPMEVENT10 0x32a
-#define CSR_MHPMEVENT11 0x32b
-#define CSR_MHPMEVENT12 0x32c
-#define CSR_MHPMEVENT13 0x32d
-#define CSR_MHPMEVENT14 0x32e
-#define CSR_MHPMEVENT15 0x32f
-#define CSR_MHPMEVENT16 0x330
-#define CSR_MHPMEVENT17 0x331
-#define CSR_MHPMEVENT18 0x332
-#define CSR_MHPMEVENT19 0x333
-#define CSR_MHPMEVENT20 0x334
-#define CSR_MHPMEVENT21 0x335
-#define CSR_MHPMEVENT22 0x336
-#define CSR_MHPMEVENT23 0x337
-#define CSR_MHPMEVENT24 0x338
-#define CSR_MHPMEVENT25 0x339
-#define CSR_MHPMEVENT26 0x33a
-#define CSR_MHPMEVENT27 0x33b
-#define CSR_MHPMEVENT28 0x33c
-#define CSR_MHPMEVENT29 0x33d
-#define CSR_MHPMEVENT30 0x33e
-#define CSR_MHPMEVENT31 0x33f
-#define CSR_MVENDORID 0xf11
-#define CSR_MARCHID 0xf12
-#define CSR_MIMPID 0xf13
-#define CSR_MHARTID 0xf14
-#define CSR_CYCLEH 0xc80
-#define CSR_TIMEH 0xc81
-#define CSR_INSTRETH 0xc82
-#define CSR_HPMCOUNTER3H 0xc83
-#define CSR_HPMCOUNTER4H 0xc84
-#define CSR_HPMCOUNTER5H 0xc85
-#define CSR_HPMCOUNTER6H 0xc86
-#define CSR_HPMCOUNTER7H 0xc87
-#define CSR_HPMCOUNTER8H 0xc88
-#define CSR_HPMCOUNTER9H 0xc89
-#define CSR_HPMCOUNTER10H 0xc8a
-#define CSR_HPMCOUNTER11H 0xc8b
-#define CSR_HPMCOUNTER12H 0xc8c
-#define CSR_HPMCOUNTER13H 0xc8d
-#define CSR_HPMCOUNTER14H 0xc8e
-#define CSR_HPMCOUNTER15H 0xc8f
-#define CSR_HPMCOUNTER16H 0xc90
-#define CSR_HPMCOUNTER17H 0xc91
-#define CSR_HPMCOUNTER18H 0xc92
-#define CSR_HPMCOUNTER19H 0xc93
-#define CSR_HPMCOUNTER20H 0xc94
-#define CSR_HPMCOUNTER21H 0xc95
-#define CSR_HPMCOUNTER22H 0xc96
-#define CSR_HPMCOUNTER23H 0xc97
-#define CSR_HPMCOUNTER24H 0xc98
-#define CSR_HPMCOUNTER25H 0xc99
-#define CSR_HPMCOUNTER26H 0xc9a
-#define CSR_HPMCOUNTER27H 0xc9b
-#define CSR_HPMCOUNTER28H 0xc9c
-#define CSR_HPMCOUNTER29H 0xc9d
-#define CSR_HPMCOUNTER30H 0xc9e
-#define CSR_HPMCOUNTER31H 0xc9f
-#define CSR_MCYCLEH 0xb80
-#define CSR_MINSTRETH 0xb82
-#define CSR_MHPMCOUNTER3H 0xb83
-#define CSR_MHPMCOUNTER4H 0xb84
-#define CSR_MHPMCOUNTER5H 0xb85
-#define CSR_MHPMCOUNTER6H 0xb86
-#define CSR_MHPMCOUNTER7H 0xb87
-#define CSR_MHPMCOUNTER8H 0xb88
-#define CSR_MHPMCOUNTER9H 0xb89
-#define CSR_MHPMCOUNTER10H 0xb8a
-#define CSR_MHPMCOUNTER11H 0xb8b
-#define CSR_MHPMCOUNTER12H 0xb8c
-#define CSR_MHPMCOUNTER13H 0xb8d
-#define CSR_MHPMCOUNTER14H 0xb8e
-#define CSR_MHPMCOUNTER15H 0xb8f
-#define CSR_MHPMCOUNTER16H 0xb90
-#define CSR_MHPMCOUNTER17H 0xb91
-#define CSR_MHPMCOUNTER18H 0xb92
-#define CSR_MHPMCOUNTER19H 0xb93
-#define CSR_MHPMCOUNTER20H 0xb94
-#define CSR_MHPMCOUNTER21H 0xb95
-#define CSR_MHPMCOUNTER22H 0xb96
-#define CSR_MHPMCOUNTER23H 0xb97
-#define CSR_MHPMCOUNTER24H 0xb98
-#define CSR_MHPMCOUNTER25H 0xb99
-#define CSR_MHPMCOUNTER26H 0xb9a
-#define CSR_MHPMCOUNTER27H 0xb9b
-#define CSR_MHPMCOUNTER28H 0xb9c
-#define CSR_MHPMCOUNTER29H 0xb9d
-#define CSR_MHPMCOUNTER30H 0xb9e
-#define CSR_MHPMCOUNTER31H 0xb9f
-
-/* mstatus bits */
+/* Floating point round mode */
+#define FSR_RD_SHIFT 5
+#define FSR_RD (0x7 << FSR_RD_SHIFT)
+
+/* Floating point accrued exception flags */
+#define FPEXC_NX 0x01
+#define FPEXC_UF 0x02
+#define FPEXC_OF 0x04
+#define FPEXC_DZ 0x08
+#define FPEXC_NV 0x10
+
+/* Floating point status register bits */
+#define FSR_AEXC_SHIFT 0
+#define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT)
+#define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT)
+#define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT)
+#define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT)
+#define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
+#define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
+
+/* Control and Status Registers */
+
+/* User Trap Setup */
+#define CSR_USTATUS 0x000
+#define CSR_UIE 0x004
+#define CSR_UTVEC 0x005
+
+/* User Trap Handling */
+#define CSR_USCRATCH 0x040
+#define CSR_UEPC 0x041
+#define CSR_UCAUSE 0x042
+#define CSR_UTVAL 0x043
+#define CSR_UIP 0x044
+
+/* User Floating-Point CSRs */
+#define CSR_FFLAGS 0x001
+#define CSR_FRM 0x002
+#define CSR_FCSR 0x003
+
+/* User Timers and Counters */
+#define CSR_CYCLE 0xc00
+#define CSR_TIME 0xc01
+#define CSR_INSTRET 0xc02
+#define CSR_HPMCOUNTER3 0xc03
+#define CSR_HPMCOUNTER4 0xc04
+#define CSR_HPMCOUNTER5 0xc05
+#define CSR_HPMCOUNTER6 0xc06
+#define CSR_HPMCOUNTER7 0xc07
+#define CSR_HPMCOUNTER8 0xc08
+#define CSR_HPMCOUNTER9 0xc09
+#define CSR_HPMCOUNTER10 0xc0a
+#define CSR_HPMCOUNTER11 0xc0b
+#define CSR_HPMCOUNTER12 0xc0c
+#define CSR_HPMCOUNTER13 0xc0d
+#define CSR_HPMCOUNTER14 0xc0e
+#define CSR_HPMCOUNTER15 0xc0f
+#define CSR_HPMCOUNTER16 0xc10
+#define CSR_HPMCOUNTER17 0xc11
+#define CSR_HPMCOUNTER18 0xc12
+#define CSR_HPMCOUNTER19 0xc13
+#define CSR_HPMCOUNTER20 0xc14
+#define CSR_HPMCOUNTER21 0xc15
+#define CSR_HPMCOUNTER22 0xc16
+#define CSR_HPMCOUNTER23 0xc17
+#define CSR_HPMCOUNTER24 0xc18
+#define CSR_HPMCOUNTER25 0xc19
+#define CSR_HPMCOUNTER26 0xc1a
+#define CSR_HPMCOUNTER27 0xc1b
+#define CSR_HPMCOUNTER28 0xc1c
+#define CSR_HPMCOUNTER29 0xc1d
+#define CSR_HPMCOUNTER30 0xc1e
+#define CSR_HPMCOUNTER31 0xc1f
+#define CSR_CYCLEH 0xc80
+#define CSR_TIMEH 0xc81
+#define CSR_INSTRETH 0xc82
+#define CSR_HPMCOUNTER3H 0xc83
+#define CSR_HPMCOUNTER4H 0xc84
+#define CSR_HPMCOUNTER5H 0xc85
+#define CSR_HPMCOUNTER6H 0xc86
+#define CSR_HPMCOUNTER7H 0xc87
+#define CSR_HPMCOUNTER8H 0xc88
+#define CSR_HPMCOUNTER9H 0xc89
+#define CSR_HPMCOUNTER10H 0xc8a
+#define CSR_HPMCOUNTER11H 0xc8b
+#define CSR_HPMCOUNTER12H 0xc8c
+#define CSR_HPMCOUNTER13H 0xc8d
+#define CSR_HPMCOUNTER14H 0xc8e
+#define CSR_HPMCOUNTER15H 0xc8f
+#define CSR_HPMCOUNTER16H 0xc90
+#define CSR_HPMCOUNTER17H 0xc91
+#define CSR_HPMCOUNTER18H 0xc92
+#define CSR_HPMCOUNTER19H 0xc93
+#define CSR_HPMCOUNTER20H 0xc94
+#define CSR_HPMCOUNTER21H 0xc95
+#define CSR_HPMCOUNTER22H 0xc96
+#define CSR_HPMCOUNTER23H 0xc97
+#define CSR_HPMCOUNTER24H 0xc98
+#define CSR_HPMCOUNTER25H 0xc99
+#define CSR_HPMCOUNTER26H 0xc9a
+#define CSR_HPMCOUNTER27H 0xc9b
+#define CSR_HPMCOUNTER28H 0xc9c
+#define CSR_HPMCOUNTER29H 0xc9d
+#define CSR_HPMCOUNTER30H 0xc9e
+#define CSR_HPMCOUNTER31H 0xc9f
+
+/* Machine Timers and Counters */
+#define CSR_MCYCLE 0xb00
+#define CSR_MINSTRET 0xb02
+#define CSR_MCYCLEH 0xb80
+#define CSR_MINSTRETH 0xb82
+
+/* Machine Information Registers */
+#define CSR_MVENDORID 0xf11
+#define CSR_MARCHID 0xf12
+#define CSR_MIMPID 0xf13
+#define CSR_MHARTID 0xf14
+
+/* Machine Trap Setup */
+#define CSR_MSTATUS 0x300
+#define CSR_MISA 0x301
+#define CSR_MEDELEG 0x302
+#define CSR_MIDELEG 0x303
+#define CSR_MIE 0x304
+#define CSR_MTVEC 0x305
+#define CSR_MCOUNTEREN 0x306
+
+/* Legacy Counter Setup (priv v1.9.1) */
+#define CSR_MUCOUNTEREN 0x320
+#define CSR_MSCOUNTEREN 0x321
+
+/* Machine Trap Handling */
+#define CSR_MSCRATCH 0x340
+#define CSR_MEPC 0x341
+#define CSR_MCAUSE 0x342
+#define CSR_MBADADDR 0x343
+#define CSR_MIP 0x344
+
+/* Supervisor Trap Setup */
+#define CSR_SSTATUS 0x100
+#define CSR_SIE 0x104
+#define CSR_STVEC 0x105
+#define CSR_SCOUNTEREN 0x106
+
+/* Supervisor Trap Handling */
+#define CSR_SSCRATCH 0x140
+#define CSR_SEPC 0x141
+#define CSR_SCAUSE 0x142
+#define CSR_SBADADDR 0x143
+#define CSR_SIP 0x144
+
+/* Supervisor Protection and Translation */
+#define CSR_SPTBR 0x180
+#define CSR_SATP 0x180
+
+/* Physical Memory Protection */
+#define CSR_PMPCFG0 0x3a0
+#define CSR_PMPCFG1 0x3a1
+#define CSR_PMPCFG2 0x3a2
+#define CSR_PMPCFG3 0x3a3
+#define CSR_PMPADDR0 0x3b0
+#define CSR_PMPADDR1 0x3b1
+#define CSR_PMPADDR2 0x3b2
+#define CSR_PMPADDR3 0x3b3
+#define CSR_PMPADDR4 0x3b4
+#define CSR_PMPADDR5 0x3b5
+#define CSR_PMPADDR6 0x3b6
+#define CSR_PMPADDR7 0x3b7
+#define CSR_PMPADDR8 0x3b8
+#define CSR_PMPADDR9 0x3b9
+#define CSR_PMPADDR10 0x3ba
+#define CSR_PMPADDR11 0x3bb
+#define CSR_PMPADDR12 0x3bc
+#define CSR_PMPADDR13 0x3bd
+#define CSR_PMPADDR14 0x3be
+#define CSR_PMPADDR15 0x3bf
+
+/* Debug/Trace Registers (shared with Debug Mode) */
+#define CSR_TSELECT 0x7a0
+#define CSR_TDATA1 0x7a1
+#define CSR_TDATA2 0x7a2
+#define CSR_TDATA3 0x7a3
+
+/* Debug Mode Registers */
+#define CSR_DCSR 0x7b0
+#define CSR_DPC 0x7b1
+#define CSR_DSCRATCH 0x7b2
+
+/* Performance Counters */
+#define CSR_MHPMCOUNTER3 0xb03
+#define CSR_MHPMCOUNTER4 0xb04
+#define CSR_MHPMCOUNTER5 0xb05
+#define CSR_MHPMCOUNTER6 0xb06
+#define CSR_MHPMCOUNTER7 0xb07
+#define CSR_MHPMCOUNTER8 0xb08
+#define CSR_MHPMCOUNTER9 0xb09
+#define CSR_MHPMCOUNTER10 0xb0a
+#define CSR_MHPMCOUNTER11 0xb0b
+#define CSR_MHPMCOUNTER12 0xb0c
+#define CSR_MHPMCOUNTER13 0xb0d
+#define CSR_MHPMCOUNTER14 0xb0e
+#define CSR_MHPMCOUNTER15 0xb0f
+#define CSR_MHPMCOUNTER16 0xb10
+#define CSR_MHPMCOUNTER17 0xb11
+#define CSR_MHPMCOUNTER18 0xb12
+#define CSR_MHPMCOUNTER19 0xb13
+#define CSR_MHPMCOUNTER20 0xb14
+#define CSR_MHPMCOUNTER21 0xb15
+#define CSR_MHPMCOUNTER22 0xb16
+#define CSR_MHPMCOUNTER23 0xb17
+#define CSR_MHPMCOUNTER24 0xb18
+#define CSR_MHPMCOUNTER25 0xb19
+#define CSR_MHPMCOUNTER26 0xb1a
+#define CSR_MHPMCOUNTER27 0xb1b
+#define CSR_MHPMCOUNTER28 0xb1c
+#define CSR_MHPMCOUNTER29 0xb1d
+#define CSR_MHPMCOUNTER30 0xb1e
+#define CSR_MHPMCOUNTER31 0xb1f
+#define CSR_MHPMEVENT3 0x323
+#define CSR_MHPMEVENT4 0x324
+#define CSR_MHPMEVENT5 0x325
+#define CSR_MHPMEVENT6 0x326
+#define CSR_MHPMEVENT7 0x327
+#define CSR_MHPMEVENT8 0x328
+#define CSR_MHPMEVENT9 0x329
+#define CSR_MHPMEVENT10 0x32a
+#define CSR_MHPMEVENT11 0x32b
+#define CSR_MHPMEVENT12 0x32c
+#define CSR_MHPMEVENT13 0x32d
+#define CSR_MHPMEVENT14 0x32e
+#define CSR_MHPMEVENT15 0x32f
+#define CSR_MHPMEVENT16 0x330
+#define CSR_MHPMEVENT17 0x331
+#define CSR_MHPMEVENT18 0x332
+#define CSR_MHPMEVENT19 0x333
+#define CSR_MHPMEVENT20 0x334
+#define CSR_MHPMEVENT21 0x335
+#define CSR_MHPMEVENT22 0x336
+#define CSR_MHPMEVENT23 0x337
+#define CSR_MHPMEVENT24 0x338
+#define CSR_MHPMEVENT25 0x339
+#define CSR_MHPMEVENT26 0x33a
+#define CSR_MHPMEVENT27 0x33b
+#define CSR_MHPMEVENT28 0x33c
+#define CSR_MHPMEVENT29 0x33d
+#define CSR_MHPMEVENT30 0x33e
+#define CSR_MHPMEVENT31 0x33f
+#define CSR_MHPMCOUNTER3H 0xb83
+#define CSR_MHPMCOUNTER4H 0xb84
+#define CSR_MHPMCOUNTER5H 0xb85
+#define CSR_MHPMCOUNTER6H 0xb86
+#define CSR_MHPMCOUNTER7H 0xb87
+#define CSR_MHPMCOUNTER8H 0xb88
+#define CSR_MHPMCOUNTER9H 0xb89
+#define CSR_MHPMCOUNTER10H 0xb8a
+#define CSR_MHPMCOUNTER11H 0xb8b
+#define CSR_MHPMCOUNTER12H 0xb8c
+#define CSR_MHPMCOUNTER13H 0xb8d
+#define CSR_MHPMCOUNTER14H 0xb8e
+#define CSR_MHPMCOUNTER15H 0xb8f
+#define CSR_MHPMCOUNTER16H 0xb90
+#define CSR_MHPMCOUNTER17H 0xb91
+#define CSR_MHPMCOUNTER18H 0xb92
+#define CSR_MHPMCOUNTER19H 0xb93
+#define CSR_MHPMCOUNTER20H 0xb94
+#define CSR_MHPMCOUNTER21H 0xb95
+#define CSR_MHPMCOUNTER22H 0xb96
+#define CSR_MHPMCOUNTER23H 0xb97
+#define CSR_MHPMCOUNTER24H 0xb98
+#define CSR_MHPMCOUNTER25H 0xb99
+#define CSR_MHPMCOUNTER26H 0xb9a
+#define CSR_MHPMCOUNTER27H 0xb9b
+#define CSR_MHPMCOUNTER28H 0xb9c
+#define CSR_MHPMCOUNTER29H 0xb9d
+#define CSR_MHPMCOUNTER30H 0xb9e
+#define CSR_MHPMCOUNTER31H 0xb9f
+
+/* mstatus CSR bits */
#define MSTATUS_UIE 0x00000001
#define MSTATUS_SIE 0x00000002
#define MSTATUS_HIE 0x00000004
@@ -276,7 +317,7 @@
#define MSTATUS_SD MSTATUS64_SD
#endif
-/* sstatus bits */
+/* sstatus CSR bits */
#define SSTATUS_UIE 0x00000001
#define SSTATUS_SIE 0x00000002
#define SSTATUS_UPIE 0x00000010
@@ -297,83 +338,71 @@
#define SSTATUS_SD SSTATUS64_SD
#endif
-/* irqs */
-#define MIP_SSIP (1 << IRQ_S_SOFT)
-#define MIP_HSIP (1 << IRQ_H_SOFT)
-#define MIP_MSIP (1 << IRQ_M_SOFT)
-#define MIP_STIP (1 << IRQ_S_TIMER)
-#define MIP_HTIP (1 << IRQ_H_TIMER)
-#define MIP_MTIP (1 << IRQ_M_TIMER)
-#define MIP_SEIP (1 << IRQ_S_EXT)
-#define MIP_HEIP (1 << IRQ_H_EXT)
-#define MIP_MEIP (1 << IRQ_M_EXT)
-
-#define SIP_SSIP MIP_SSIP
-#define SIP_STIP MIP_STIP
-#define SIP_SEIP MIP_SEIP
-
+/* Privilege modes */
#define PRV_U 0
#define PRV_S 1
#define PRV_H 2
#define PRV_M 3
-/* privileged ISA 1.9.1 VM modes (mstatus.vm) */
-#define VM_1_09_MBARE 0
-#define VM_1_09_MBB 1
-#define VM_1_09_MBBID 2
-#define VM_1_09_SV32 8
-#define VM_1_09_SV39 9
-#define VM_1_09_SV48 10
-
-/* privileged ISA 1.10.0 VM modes (satp.mode) */
-#define VM_1_10_MBARE 0
-#define VM_1_10_SV32 1
-#define VM_1_10_SV39 8
-#define VM_1_10_SV48 9
-#define VM_1_10_SV57 10
-#define VM_1_10_SV64 11
-
-/* privileged ISA interrupt causes */
-#define IRQ_U_SOFT 0 /* since: priv-1.10 */
-#define IRQ_S_SOFT 1
-#define IRQ_H_SOFT 2 /* until: priv-1.9.1 */
-#define IRQ_M_SOFT 3 /* until: priv-1.9.1 */
-#define IRQ_U_TIMER 4 /* since: priv-1.10 */
-#define IRQ_S_TIMER 5
-#define IRQ_H_TIMER 6 /* until: priv-1.9.1 */
-#define IRQ_M_TIMER 7 /* until: priv-1.9.1 */
-#define IRQ_U_EXT 8 /* since: priv-1.10 */
-#define IRQ_S_EXT 9
-#define IRQ_H_EXT 10 /* until: priv-1.9.1 */
-#define IRQ_M_EXT 11 /* until: priv-1.9.1 */
-#define IRQ_X_COP 12 /* non-standard */
-
-/* Default addresses */
-#define DEFAULT_RSTVEC 0x00001000
-
-/* RV32 satp field masks */
-#define SATP32_MODE 0x80000000
-#define SATP32_ASID 0x7fc00000
-#define SATP32_PPN 0x003fffff
-
-/* RV64 satp field masks */
-#define SATP64_MODE 0xF000000000000000ULL
-#define SATP64_ASID 0x0FFFF00000000000ULL
-#define SATP64_PPN 0x00000FFFFFFFFFFFULL
+/* RV32 satp CSR field masks */
+#define SATP32_MODE 0x80000000
+#define SATP32_ASID 0x7fc00000
+#define SATP32_PPN 0x003fffff
+
+/* RV64 satp CSR field masks */
+#define SATP64_MODE 0xF000000000000000ULL
+#define SATP64_ASID 0x0FFFF00000000000ULL
+#define SATP64_PPN 0x00000FFFFFFFFFFFULL
#if defined(TARGET_RISCV32)
-#define SATP_MODE SATP32_MODE
-#define SATP_ASID SATP32_ASID
-#define SATP_PPN SATP32_PPN
+#define SATP_MODE SATP32_MODE
+#define SATP_ASID SATP32_ASID
+#define SATP_PPN SATP32_PPN
#endif
#if defined(TARGET_RISCV64)
-#define SATP_MODE SATP64_MODE
-#define SATP_ASID SATP64_ASID
-#define SATP_PPN SATP64_PPN
+#define SATP_MODE SATP64_MODE
+#define SATP_ASID SATP64_ASID
+#define SATP_PPN SATP64_PPN
#endif
-/* RISCV Exception Codes */
-#define EXCP_NONE -1 /* not a real RISCV exception code */
+/* VM modes (mstatus.vm) privileged ISA 1.9.1 */
+#define VM_1_09_MBARE 0
+#define VM_1_09_MBB 1
+#define VM_1_09_MBBID 2
+#define VM_1_09_SV32 8
+#define VM_1_09_SV39 9
+#define VM_1_09_SV48 10
+
+/* VM modes (satp.mode) privileged ISA 1.10 */
+#define VM_1_10_MBARE 0
+#define VM_1_10_SV32 1
+#define VM_1_10_SV39 8
+#define VM_1_10_SV48 9
+#define VM_1_10_SV57 10
+#define VM_1_10_SV64 11
+
+/* Page table entry (PTE) fields */
+#define PTE_V 0x001 /* Valid */
+#define PTE_R 0x002 /* Read */
+#define PTE_W 0x004 /* Write */
+#define PTE_X 0x008 /* Execute */
+#define PTE_U 0x010 /* User */
+#define PTE_G 0x020 /* Global */
+#define PTE_A 0x040 /* Accessed */
+#define PTE_D 0x080 /* Dirty */
+#define PTE_SOFT 0x300 /* Reserved for Software */
+
+/* Page table PPN shift amount */
+#define PTE_PPN_SHIFT 10
+
+/* Leaf page shift amount */
+#define PGSHIFT 12
+
+/* Default Reset Vector adress */
+#define DEFAULT_RSTVEC 0x1000
+
+/* Exception causes */
+#define EXCP_NONE -1 /* sentinel value */
#define RISCV_EXCP_INST_ADDR_MIS 0x0
#define RISCV_EXCP_INST_ACCESS_FAULT 0x1
#define RISCV_EXCP_ILLEGAL_INST 0x2
@@ -382,9 +411,7 @@
#define RISCV_EXCP_LOAD_ACCESS_FAULT 0x5
#define RISCV_EXCP_STORE_AMO_ADDR_MIS 0x6
#define RISCV_EXCP_STORE_AMO_ACCESS_FAULT 0x7
-#define RISCV_EXCP_U_ECALL 0x8 /* for convenience, report all
- ECALLs as this, handler
- fixes */
+#define RISCV_EXCP_U_ECALL 0x8
#define RISCV_EXCP_S_ECALL 0x9
#define RISCV_EXCP_H_ECALL 0xa
#define RISCV_EXCP_M_ECALL 0xb
@@ -395,15 +422,35 @@
#define RISCV_EXCP_INT_FLAG 0x80000000
#define RISCV_EXCP_INT_MASK 0x7fffffff
-/* page table entry (PTE) fields */
-#define PTE_V 0x001 /* Valid */
-#define PTE_R 0x002 /* Read */
-#define PTE_W 0x004 /* Write */
-#define PTE_X 0x008 /* Execute */
-#define PTE_U 0x010 /* User */
-#define PTE_G 0x020 /* Global */
-#define PTE_A 0x040 /* Accessed */
-#define PTE_D 0x080 /* Dirty */
-#define PTE_SOFT 0x300 /* Reserved for Software */
-
-#define PTE_PPN_SHIFT 10
+/* Interrupt causes */
+#define IRQ_U_SOFT 0
+#define IRQ_S_SOFT 1
+#define IRQ_H_SOFT 2 /* reserved */
+#define IRQ_M_SOFT 3
+#define IRQ_U_TIMER 4
+#define IRQ_S_TIMER 5
+#define IRQ_H_TIMER 6 /* reserved */
+#define IRQ_M_TIMER 7
+#define IRQ_U_EXT 8
+#define IRQ_S_EXT 9
+#define IRQ_H_EXT 10 /* reserved */
+#define IRQ_M_EXT 11
+
+/* mip masks */
+#define MIP_USIP (1 << IRQ_U_SOFT)
+#define MIP_SSIP (1 << IRQ_S_SOFT)
+#define MIP_HSIP (1 << IRQ_H_SOFT)
+#define MIP_MSIP (1 << IRQ_M_SOFT)
+#define MIP_UTIP (1 << IRQ_U_TIMER)
+#define MIP_STIP (1 << IRQ_S_TIMER)
+#define MIP_HTIP (1 << IRQ_H_TIMER)
+#define MIP_MTIP (1 << IRQ_M_TIMER)
+#define MIP_UEIP (1 << IRQ_U_EXT)
+#define MIP_SEIP (1 << IRQ_S_EXT)
+#define MIP_HEIP (1 << IRQ_H_EXT)
+#define MIP_MEIP (1 << IRQ_M_EXT)
+
+/* sip masks */
+#define SIP_SSIP MIP_SSIP
+#define SIP_STIP MIP_STIP
+#define SIP_SEIP MIP_SEIP
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 495390ab1c..3726299d4a 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -90,7 +90,7 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
target_ulong csrno)
{
#ifndef CONFIG_USER_ONLY
- uint64_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_X_COP);
+ uint64_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP;
uint64_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [Qemu-devel] [PATCH v1 3/5] RISC-V: Update CSR and interrupt definitions
2018-10-08 18:25 ` [Qemu-devel] [PATCH v1 3/5] RISC-V: Update CSR and interrupt definitions Alistair Francis
@ 2018-10-10 20:03 ` Palmer Dabbelt
0 siblings, 0 replies; 25+ messages in thread
From: Palmer Dabbelt @ 2018-10-10 20:03 UTC (permalink / raw)
Cc: qemu-devel, Michael Clark, alistair23, Alistair.Francis
On Mon, 08 Oct 2018 11:25:36 PDT (-0700), Alistair.Francis@wdc.com wrote:
> From: Michael Clark <mjc@sifive.com>
>
> * Add user-mode CSR defininitions.
> * Reorder CSR definitions to match the specification.
> * Change H mode interrupt comment to 'reserved'.
> * Remove unused X_COP interrupt.
> * Add user-mode interrupts.
> * Remove erroneous until comments on machine mode interrupts.
> * Move together paging mode and page table bit definitions.
> * Move together interrupt and exception cause definitions.
>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.c | 6 +-
> target/riscv/cpu_bits.h | 683 +++++++++++++++++++++------------------
> target/riscv/op_helper.c | 2 +-
> 3 files changed, 370 insertions(+), 321 deletions(-)
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d630e8fd6c..a025a0a3ba 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -74,8 +74,10 @@ const char * const riscv_intr_names[] = {
> "s_external",
> "h_external",
> "m_external",
> - "coprocessor",
> - "host"
> + "reserved",
> + "reserved",
> + "reserved",
> + "reserved"
> };
>
> typedef struct RISCVCPUInfo {
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 12b4757088..5439f4719e 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -6,242 +6,283 @@
> (((target_ulong)(val) * ((mask) & ~((mask) << 1))) & \
> (target_ulong)(mask)))
>
> -#define PGSHIFT 12
> -
> -#define FSR_RD_SHIFT 5
> -#define FSR_RD (0x7 << FSR_RD_SHIFT)
> -
> -#define FPEXC_NX 0x01
> -#define FPEXC_UF 0x02
> -#define FPEXC_OF 0x04
> -#define FPEXC_DZ 0x08
> -#define FPEXC_NV 0x10
> -
> -#define FSR_AEXC_SHIFT 0
> -#define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT)
> -#define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT)
> -#define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT)
> -#define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT)
> -#define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
> -#define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
> -
> -/* CSR numbers */
> -#define CSR_FFLAGS 0x1
> -#define CSR_FRM 0x2
> -#define CSR_FCSR 0x3
> -#define CSR_CYCLE 0xc00
> -#define CSR_TIME 0xc01
> -#define CSR_INSTRET 0xc02
> -#define CSR_HPMCOUNTER3 0xc03
> -#define CSR_HPMCOUNTER4 0xc04
> -#define CSR_HPMCOUNTER5 0xc05
> -#define CSR_HPMCOUNTER6 0xc06
> -#define CSR_HPMCOUNTER7 0xc07
> -#define CSR_HPMCOUNTER8 0xc08
> -#define CSR_HPMCOUNTER9 0xc09
> -#define CSR_HPMCOUNTER10 0xc0a
> -#define CSR_HPMCOUNTER11 0xc0b
> -#define CSR_HPMCOUNTER12 0xc0c
> -#define CSR_HPMCOUNTER13 0xc0d
> -#define CSR_HPMCOUNTER14 0xc0e
> -#define CSR_HPMCOUNTER15 0xc0f
> -#define CSR_HPMCOUNTER16 0xc10
> -#define CSR_HPMCOUNTER17 0xc11
> -#define CSR_HPMCOUNTER18 0xc12
> -#define CSR_HPMCOUNTER19 0xc13
> -#define CSR_HPMCOUNTER20 0xc14
> -#define CSR_HPMCOUNTER21 0xc15
> -#define CSR_HPMCOUNTER22 0xc16
> -#define CSR_HPMCOUNTER23 0xc17
> -#define CSR_HPMCOUNTER24 0xc18
> -#define CSR_HPMCOUNTER25 0xc19
> -#define CSR_HPMCOUNTER26 0xc1a
> -#define CSR_HPMCOUNTER27 0xc1b
> -#define CSR_HPMCOUNTER28 0xc1c
> -#define CSR_HPMCOUNTER29 0xc1d
> -#define CSR_HPMCOUNTER30 0xc1e
> -#define CSR_HPMCOUNTER31 0xc1f
> -#define CSR_SSTATUS 0x100
> -#define CSR_SIE 0x104
> -#define CSR_STVEC 0x105
> -#define CSR_SCOUNTEREN 0x106
> -#define CSR_SSCRATCH 0x140
> -#define CSR_SEPC 0x141
> -#define CSR_SCAUSE 0x142
> -#define CSR_SBADADDR 0x143
> -#define CSR_SIP 0x144
> -#define CSR_SPTBR 0x180
> -#define CSR_SATP 0x180
> -#define CSR_MSTATUS 0x300
> -#define CSR_MISA 0x301
> -#define CSR_MEDELEG 0x302
> -#define CSR_MIDELEG 0x303
> -#define CSR_MIE 0x304
> -#define CSR_MTVEC 0x305
> -#define CSR_MCOUNTEREN 0x306
> -#define CSR_MSCRATCH 0x340
> -#define CSR_MEPC 0x341
> -#define CSR_MCAUSE 0x342
> -#define CSR_MBADADDR 0x343
> -#define CSR_MIP 0x344
> -#define CSR_PMPCFG0 0x3a0
> -#define CSR_PMPCFG1 0x3a1
> -#define CSR_PMPCFG2 0x3a2
> -#define CSR_PMPCFG3 0x3a3
> -#define CSR_PMPADDR0 0x3b0
> -#define CSR_PMPADDR1 0x3b1
> -#define CSR_PMPADDR2 0x3b2
> -#define CSR_PMPADDR3 0x3b3
> -#define CSR_PMPADDR4 0x3b4
> -#define CSR_PMPADDR5 0x3b5
> -#define CSR_PMPADDR6 0x3b6
> -#define CSR_PMPADDR7 0x3b7
> -#define CSR_PMPADDR8 0x3b8
> -#define CSR_PMPADDR9 0x3b9
> -#define CSR_PMPADDR10 0x3ba
> -#define CSR_PMPADDR11 0x3bb
> -#define CSR_PMPADDR12 0x3bc
> -#define CSR_PMPADDR13 0x3bd
> -#define CSR_PMPADDR14 0x3be
> -#define CSR_PMPADDR15 0x3bf
> -#define CSR_TSELECT 0x7a0
> -#define CSR_TDATA1 0x7a1
> -#define CSR_TDATA2 0x7a2
> -#define CSR_TDATA3 0x7a3
> -#define CSR_DCSR 0x7b0
> -#define CSR_DPC 0x7b1
> -#define CSR_DSCRATCH 0x7b2
> -#define CSR_MCYCLE 0xb00
> -#define CSR_MINSTRET 0xb02
> -#define CSR_MHPMCOUNTER3 0xb03
> -#define CSR_MHPMCOUNTER4 0xb04
> -#define CSR_MHPMCOUNTER5 0xb05
> -#define CSR_MHPMCOUNTER6 0xb06
> -#define CSR_MHPMCOUNTER7 0xb07
> -#define CSR_MHPMCOUNTER8 0xb08
> -#define CSR_MHPMCOUNTER9 0xb09
> -#define CSR_MHPMCOUNTER10 0xb0a
> -#define CSR_MHPMCOUNTER11 0xb0b
> -#define CSR_MHPMCOUNTER12 0xb0c
> -#define CSR_MHPMCOUNTER13 0xb0d
> -#define CSR_MHPMCOUNTER14 0xb0e
> -#define CSR_MHPMCOUNTER15 0xb0f
> -#define CSR_MHPMCOUNTER16 0xb10
> -#define CSR_MHPMCOUNTER17 0xb11
> -#define CSR_MHPMCOUNTER18 0xb12
> -#define CSR_MHPMCOUNTER19 0xb13
> -#define CSR_MHPMCOUNTER20 0xb14
> -#define CSR_MHPMCOUNTER21 0xb15
> -#define CSR_MHPMCOUNTER22 0xb16
> -#define CSR_MHPMCOUNTER23 0xb17
> -#define CSR_MHPMCOUNTER24 0xb18
> -#define CSR_MHPMCOUNTER25 0xb19
> -#define CSR_MHPMCOUNTER26 0xb1a
> -#define CSR_MHPMCOUNTER27 0xb1b
> -#define CSR_MHPMCOUNTER28 0xb1c
> -#define CSR_MHPMCOUNTER29 0xb1d
> -#define CSR_MHPMCOUNTER30 0xb1e
> -#define CSR_MHPMCOUNTER31 0xb1f
> -#define CSR_MUCOUNTEREN 0x320
> -#define CSR_MSCOUNTEREN 0x321
> -#define CSR_MHPMEVENT3 0x323
> -#define CSR_MHPMEVENT4 0x324
> -#define CSR_MHPMEVENT5 0x325
> -#define CSR_MHPMEVENT6 0x326
> -#define CSR_MHPMEVENT7 0x327
> -#define CSR_MHPMEVENT8 0x328
> -#define CSR_MHPMEVENT9 0x329
> -#define CSR_MHPMEVENT10 0x32a
> -#define CSR_MHPMEVENT11 0x32b
> -#define CSR_MHPMEVENT12 0x32c
> -#define CSR_MHPMEVENT13 0x32d
> -#define CSR_MHPMEVENT14 0x32e
> -#define CSR_MHPMEVENT15 0x32f
> -#define CSR_MHPMEVENT16 0x330
> -#define CSR_MHPMEVENT17 0x331
> -#define CSR_MHPMEVENT18 0x332
> -#define CSR_MHPMEVENT19 0x333
> -#define CSR_MHPMEVENT20 0x334
> -#define CSR_MHPMEVENT21 0x335
> -#define CSR_MHPMEVENT22 0x336
> -#define CSR_MHPMEVENT23 0x337
> -#define CSR_MHPMEVENT24 0x338
> -#define CSR_MHPMEVENT25 0x339
> -#define CSR_MHPMEVENT26 0x33a
> -#define CSR_MHPMEVENT27 0x33b
> -#define CSR_MHPMEVENT28 0x33c
> -#define CSR_MHPMEVENT29 0x33d
> -#define CSR_MHPMEVENT30 0x33e
> -#define CSR_MHPMEVENT31 0x33f
> -#define CSR_MVENDORID 0xf11
> -#define CSR_MARCHID 0xf12
> -#define CSR_MIMPID 0xf13
> -#define CSR_MHARTID 0xf14
> -#define CSR_CYCLEH 0xc80
> -#define CSR_TIMEH 0xc81
> -#define CSR_INSTRETH 0xc82
> -#define CSR_HPMCOUNTER3H 0xc83
> -#define CSR_HPMCOUNTER4H 0xc84
> -#define CSR_HPMCOUNTER5H 0xc85
> -#define CSR_HPMCOUNTER6H 0xc86
> -#define CSR_HPMCOUNTER7H 0xc87
> -#define CSR_HPMCOUNTER8H 0xc88
> -#define CSR_HPMCOUNTER9H 0xc89
> -#define CSR_HPMCOUNTER10H 0xc8a
> -#define CSR_HPMCOUNTER11H 0xc8b
> -#define CSR_HPMCOUNTER12H 0xc8c
> -#define CSR_HPMCOUNTER13H 0xc8d
> -#define CSR_HPMCOUNTER14H 0xc8e
> -#define CSR_HPMCOUNTER15H 0xc8f
> -#define CSR_HPMCOUNTER16H 0xc90
> -#define CSR_HPMCOUNTER17H 0xc91
> -#define CSR_HPMCOUNTER18H 0xc92
> -#define CSR_HPMCOUNTER19H 0xc93
> -#define CSR_HPMCOUNTER20H 0xc94
> -#define CSR_HPMCOUNTER21H 0xc95
> -#define CSR_HPMCOUNTER22H 0xc96
> -#define CSR_HPMCOUNTER23H 0xc97
> -#define CSR_HPMCOUNTER24H 0xc98
> -#define CSR_HPMCOUNTER25H 0xc99
> -#define CSR_HPMCOUNTER26H 0xc9a
> -#define CSR_HPMCOUNTER27H 0xc9b
> -#define CSR_HPMCOUNTER28H 0xc9c
> -#define CSR_HPMCOUNTER29H 0xc9d
> -#define CSR_HPMCOUNTER30H 0xc9e
> -#define CSR_HPMCOUNTER31H 0xc9f
> -#define CSR_MCYCLEH 0xb80
> -#define CSR_MINSTRETH 0xb82
> -#define CSR_MHPMCOUNTER3H 0xb83
> -#define CSR_MHPMCOUNTER4H 0xb84
> -#define CSR_MHPMCOUNTER5H 0xb85
> -#define CSR_MHPMCOUNTER6H 0xb86
> -#define CSR_MHPMCOUNTER7H 0xb87
> -#define CSR_MHPMCOUNTER8H 0xb88
> -#define CSR_MHPMCOUNTER9H 0xb89
> -#define CSR_MHPMCOUNTER10H 0xb8a
> -#define CSR_MHPMCOUNTER11H 0xb8b
> -#define CSR_MHPMCOUNTER12H 0xb8c
> -#define CSR_MHPMCOUNTER13H 0xb8d
> -#define CSR_MHPMCOUNTER14H 0xb8e
> -#define CSR_MHPMCOUNTER15H 0xb8f
> -#define CSR_MHPMCOUNTER16H 0xb90
> -#define CSR_MHPMCOUNTER17H 0xb91
> -#define CSR_MHPMCOUNTER18H 0xb92
> -#define CSR_MHPMCOUNTER19H 0xb93
> -#define CSR_MHPMCOUNTER20H 0xb94
> -#define CSR_MHPMCOUNTER21H 0xb95
> -#define CSR_MHPMCOUNTER22H 0xb96
> -#define CSR_MHPMCOUNTER23H 0xb97
> -#define CSR_MHPMCOUNTER24H 0xb98
> -#define CSR_MHPMCOUNTER25H 0xb99
> -#define CSR_MHPMCOUNTER26H 0xb9a
> -#define CSR_MHPMCOUNTER27H 0xb9b
> -#define CSR_MHPMCOUNTER28H 0xb9c
> -#define CSR_MHPMCOUNTER29H 0xb9d
> -#define CSR_MHPMCOUNTER30H 0xb9e
> -#define CSR_MHPMCOUNTER31H 0xb9f
> -
> -/* mstatus bits */
> +/* Floating point round mode */
> +#define FSR_RD_SHIFT 5
> +#define FSR_RD (0x7 << FSR_RD_SHIFT)
> +
> +/* Floating point accrued exception flags */
> +#define FPEXC_NX 0x01
> +#define FPEXC_UF 0x02
> +#define FPEXC_OF 0x04
> +#define FPEXC_DZ 0x08
> +#define FPEXC_NV 0x10
> +
> +/* Floating point status register bits */
> +#define FSR_AEXC_SHIFT 0
> +#define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT)
> +#define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT)
> +#define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT)
> +#define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT)
> +#define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
> +#define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
> +
> +/* Control and Status Registers */
> +
> +/* User Trap Setup */
> +#define CSR_USTATUS 0x000
> +#define CSR_UIE 0x004
> +#define CSR_UTVEC 0x005
> +
> +/* User Trap Handling */
> +#define CSR_USCRATCH 0x040
> +#define CSR_UEPC 0x041
> +#define CSR_UCAUSE 0x042
> +#define CSR_UTVAL 0x043
> +#define CSR_UIP 0x044
> +
> +/* User Floating-Point CSRs */
> +#define CSR_FFLAGS 0x001
> +#define CSR_FRM 0x002
> +#define CSR_FCSR 0x003
> +
> +/* User Timers and Counters */
> +#define CSR_CYCLE 0xc00
> +#define CSR_TIME 0xc01
> +#define CSR_INSTRET 0xc02
> +#define CSR_HPMCOUNTER3 0xc03
> +#define CSR_HPMCOUNTER4 0xc04
> +#define CSR_HPMCOUNTER5 0xc05
> +#define CSR_HPMCOUNTER6 0xc06
> +#define CSR_HPMCOUNTER7 0xc07
> +#define CSR_HPMCOUNTER8 0xc08
> +#define CSR_HPMCOUNTER9 0xc09
> +#define CSR_HPMCOUNTER10 0xc0a
> +#define CSR_HPMCOUNTER11 0xc0b
> +#define CSR_HPMCOUNTER12 0xc0c
> +#define CSR_HPMCOUNTER13 0xc0d
> +#define CSR_HPMCOUNTER14 0xc0e
> +#define CSR_HPMCOUNTER15 0xc0f
> +#define CSR_HPMCOUNTER16 0xc10
> +#define CSR_HPMCOUNTER17 0xc11
> +#define CSR_HPMCOUNTER18 0xc12
> +#define CSR_HPMCOUNTER19 0xc13
> +#define CSR_HPMCOUNTER20 0xc14
> +#define CSR_HPMCOUNTER21 0xc15
> +#define CSR_HPMCOUNTER22 0xc16
> +#define CSR_HPMCOUNTER23 0xc17
> +#define CSR_HPMCOUNTER24 0xc18
> +#define CSR_HPMCOUNTER25 0xc19
> +#define CSR_HPMCOUNTER26 0xc1a
> +#define CSR_HPMCOUNTER27 0xc1b
> +#define CSR_HPMCOUNTER28 0xc1c
> +#define CSR_HPMCOUNTER29 0xc1d
> +#define CSR_HPMCOUNTER30 0xc1e
> +#define CSR_HPMCOUNTER31 0xc1f
> +#define CSR_CYCLEH 0xc80
> +#define CSR_TIMEH 0xc81
> +#define CSR_INSTRETH 0xc82
> +#define CSR_HPMCOUNTER3H 0xc83
> +#define CSR_HPMCOUNTER4H 0xc84
> +#define CSR_HPMCOUNTER5H 0xc85
> +#define CSR_HPMCOUNTER6H 0xc86
> +#define CSR_HPMCOUNTER7H 0xc87
> +#define CSR_HPMCOUNTER8H 0xc88
> +#define CSR_HPMCOUNTER9H 0xc89
> +#define CSR_HPMCOUNTER10H 0xc8a
> +#define CSR_HPMCOUNTER11H 0xc8b
> +#define CSR_HPMCOUNTER12H 0xc8c
> +#define CSR_HPMCOUNTER13H 0xc8d
> +#define CSR_HPMCOUNTER14H 0xc8e
> +#define CSR_HPMCOUNTER15H 0xc8f
> +#define CSR_HPMCOUNTER16H 0xc90
> +#define CSR_HPMCOUNTER17H 0xc91
> +#define CSR_HPMCOUNTER18H 0xc92
> +#define CSR_HPMCOUNTER19H 0xc93
> +#define CSR_HPMCOUNTER20H 0xc94
> +#define CSR_HPMCOUNTER21H 0xc95
> +#define CSR_HPMCOUNTER22H 0xc96
> +#define CSR_HPMCOUNTER23H 0xc97
> +#define CSR_HPMCOUNTER24H 0xc98
> +#define CSR_HPMCOUNTER25H 0xc99
> +#define CSR_HPMCOUNTER26H 0xc9a
> +#define CSR_HPMCOUNTER27H 0xc9b
> +#define CSR_HPMCOUNTER28H 0xc9c
> +#define CSR_HPMCOUNTER29H 0xc9d
> +#define CSR_HPMCOUNTER30H 0xc9e
> +#define CSR_HPMCOUNTER31H 0xc9f
> +
> +/* Machine Timers and Counters */
> +#define CSR_MCYCLE 0xb00
> +#define CSR_MINSTRET 0xb02
> +#define CSR_MCYCLEH 0xb80
> +#define CSR_MINSTRETH 0xb82
> +
> +/* Machine Information Registers */
> +#define CSR_MVENDORID 0xf11
> +#define CSR_MARCHID 0xf12
> +#define CSR_MIMPID 0xf13
> +#define CSR_MHARTID 0xf14
> +
> +/* Machine Trap Setup */
> +#define CSR_MSTATUS 0x300
> +#define CSR_MISA 0x301
> +#define CSR_MEDELEG 0x302
> +#define CSR_MIDELEG 0x303
> +#define CSR_MIE 0x304
> +#define CSR_MTVEC 0x305
> +#define CSR_MCOUNTEREN 0x306
> +
> +/* Legacy Counter Setup (priv v1.9.1) */
> +#define CSR_MUCOUNTEREN 0x320
> +#define CSR_MSCOUNTEREN 0x321
> +
> +/* Machine Trap Handling */
> +#define CSR_MSCRATCH 0x340
> +#define CSR_MEPC 0x341
> +#define CSR_MCAUSE 0x342
> +#define CSR_MBADADDR 0x343
> +#define CSR_MIP 0x344
> +
> +/* Supervisor Trap Setup */
> +#define CSR_SSTATUS 0x100
> +#define CSR_SIE 0x104
> +#define CSR_STVEC 0x105
> +#define CSR_SCOUNTEREN 0x106
> +
> +/* Supervisor Trap Handling */
> +#define CSR_SSCRATCH 0x140
> +#define CSR_SEPC 0x141
> +#define CSR_SCAUSE 0x142
> +#define CSR_SBADADDR 0x143
> +#define CSR_SIP 0x144
> +
> +/* Supervisor Protection and Translation */
> +#define CSR_SPTBR 0x180
> +#define CSR_SATP 0x180
> +
> +/* Physical Memory Protection */
> +#define CSR_PMPCFG0 0x3a0
> +#define CSR_PMPCFG1 0x3a1
> +#define CSR_PMPCFG2 0x3a2
> +#define CSR_PMPCFG3 0x3a3
> +#define CSR_PMPADDR0 0x3b0
> +#define CSR_PMPADDR1 0x3b1
> +#define CSR_PMPADDR2 0x3b2
> +#define CSR_PMPADDR3 0x3b3
> +#define CSR_PMPADDR4 0x3b4
> +#define CSR_PMPADDR5 0x3b5
> +#define CSR_PMPADDR6 0x3b6
> +#define CSR_PMPADDR7 0x3b7
> +#define CSR_PMPADDR8 0x3b8
> +#define CSR_PMPADDR9 0x3b9
> +#define CSR_PMPADDR10 0x3ba
> +#define CSR_PMPADDR11 0x3bb
> +#define CSR_PMPADDR12 0x3bc
> +#define CSR_PMPADDR13 0x3bd
> +#define CSR_PMPADDR14 0x3be
> +#define CSR_PMPADDR15 0x3bf
> +
> +/* Debug/Trace Registers (shared with Debug Mode) */
> +#define CSR_TSELECT 0x7a0
> +#define CSR_TDATA1 0x7a1
> +#define CSR_TDATA2 0x7a2
> +#define CSR_TDATA3 0x7a3
> +
> +/* Debug Mode Registers */
> +#define CSR_DCSR 0x7b0
> +#define CSR_DPC 0x7b1
> +#define CSR_DSCRATCH 0x7b2
> +
> +/* Performance Counters */
> +#define CSR_MHPMCOUNTER3 0xb03
> +#define CSR_MHPMCOUNTER4 0xb04
> +#define CSR_MHPMCOUNTER5 0xb05
> +#define CSR_MHPMCOUNTER6 0xb06
> +#define CSR_MHPMCOUNTER7 0xb07
> +#define CSR_MHPMCOUNTER8 0xb08
> +#define CSR_MHPMCOUNTER9 0xb09
> +#define CSR_MHPMCOUNTER10 0xb0a
> +#define CSR_MHPMCOUNTER11 0xb0b
> +#define CSR_MHPMCOUNTER12 0xb0c
> +#define CSR_MHPMCOUNTER13 0xb0d
> +#define CSR_MHPMCOUNTER14 0xb0e
> +#define CSR_MHPMCOUNTER15 0xb0f
> +#define CSR_MHPMCOUNTER16 0xb10
> +#define CSR_MHPMCOUNTER17 0xb11
> +#define CSR_MHPMCOUNTER18 0xb12
> +#define CSR_MHPMCOUNTER19 0xb13
> +#define CSR_MHPMCOUNTER20 0xb14
> +#define CSR_MHPMCOUNTER21 0xb15
> +#define CSR_MHPMCOUNTER22 0xb16
> +#define CSR_MHPMCOUNTER23 0xb17
> +#define CSR_MHPMCOUNTER24 0xb18
> +#define CSR_MHPMCOUNTER25 0xb19
> +#define CSR_MHPMCOUNTER26 0xb1a
> +#define CSR_MHPMCOUNTER27 0xb1b
> +#define CSR_MHPMCOUNTER28 0xb1c
> +#define CSR_MHPMCOUNTER29 0xb1d
> +#define CSR_MHPMCOUNTER30 0xb1e
> +#define CSR_MHPMCOUNTER31 0xb1f
> +#define CSR_MHPMEVENT3 0x323
> +#define CSR_MHPMEVENT4 0x324
> +#define CSR_MHPMEVENT5 0x325
> +#define CSR_MHPMEVENT6 0x326
> +#define CSR_MHPMEVENT7 0x327
> +#define CSR_MHPMEVENT8 0x328
> +#define CSR_MHPMEVENT9 0x329
> +#define CSR_MHPMEVENT10 0x32a
> +#define CSR_MHPMEVENT11 0x32b
> +#define CSR_MHPMEVENT12 0x32c
> +#define CSR_MHPMEVENT13 0x32d
> +#define CSR_MHPMEVENT14 0x32e
> +#define CSR_MHPMEVENT15 0x32f
> +#define CSR_MHPMEVENT16 0x330
> +#define CSR_MHPMEVENT17 0x331
> +#define CSR_MHPMEVENT18 0x332
> +#define CSR_MHPMEVENT19 0x333
> +#define CSR_MHPMEVENT20 0x334
> +#define CSR_MHPMEVENT21 0x335
> +#define CSR_MHPMEVENT22 0x336
> +#define CSR_MHPMEVENT23 0x337
> +#define CSR_MHPMEVENT24 0x338
> +#define CSR_MHPMEVENT25 0x339
> +#define CSR_MHPMEVENT26 0x33a
> +#define CSR_MHPMEVENT27 0x33b
> +#define CSR_MHPMEVENT28 0x33c
> +#define CSR_MHPMEVENT29 0x33d
> +#define CSR_MHPMEVENT30 0x33e
> +#define CSR_MHPMEVENT31 0x33f
> +#define CSR_MHPMCOUNTER3H 0xb83
> +#define CSR_MHPMCOUNTER4H 0xb84
> +#define CSR_MHPMCOUNTER5H 0xb85
> +#define CSR_MHPMCOUNTER6H 0xb86
> +#define CSR_MHPMCOUNTER7H 0xb87
> +#define CSR_MHPMCOUNTER8H 0xb88
> +#define CSR_MHPMCOUNTER9H 0xb89
> +#define CSR_MHPMCOUNTER10H 0xb8a
> +#define CSR_MHPMCOUNTER11H 0xb8b
> +#define CSR_MHPMCOUNTER12H 0xb8c
> +#define CSR_MHPMCOUNTER13H 0xb8d
> +#define CSR_MHPMCOUNTER14H 0xb8e
> +#define CSR_MHPMCOUNTER15H 0xb8f
> +#define CSR_MHPMCOUNTER16H 0xb90
> +#define CSR_MHPMCOUNTER17H 0xb91
> +#define CSR_MHPMCOUNTER18H 0xb92
> +#define CSR_MHPMCOUNTER19H 0xb93
> +#define CSR_MHPMCOUNTER20H 0xb94
> +#define CSR_MHPMCOUNTER21H 0xb95
> +#define CSR_MHPMCOUNTER22H 0xb96
> +#define CSR_MHPMCOUNTER23H 0xb97
> +#define CSR_MHPMCOUNTER24H 0xb98
> +#define CSR_MHPMCOUNTER25H 0xb99
> +#define CSR_MHPMCOUNTER26H 0xb9a
> +#define CSR_MHPMCOUNTER27H 0xb9b
> +#define CSR_MHPMCOUNTER28H 0xb9c
> +#define CSR_MHPMCOUNTER29H 0xb9d
> +#define CSR_MHPMCOUNTER30H 0xb9e
> +#define CSR_MHPMCOUNTER31H 0xb9f
> +
> +/* mstatus CSR bits */
> #define MSTATUS_UIE 0x00000001
> #define MSTATUS_SIE 0x00000002
> #define MSTATUS_HIE 0x00000004
> @@ -276,7 +317,7 @@
> #define MSTATUS_SD MSTATUS64_SD
> #endif
>
> -/* sstatus bits */
> +/* sstatus CSR bits */
> #define SSTATUS_UIE 0x00000001
> #define SSTATUS_SIE 0x00000002
> #define SSTATUS_UPIE 0x00000010
> @@ -297,83 +338,71 @@
> #define SSTATUS_SD SSTATUS64_SD
> #endif
>
> -/* irqs */
> -#define MIP_SSIP (1 << IRQ_S_SOFT)
> -#define MIP_HSIP (1 << IRQ_H_SOFT)
> -#define MIP_MSIP (1 << IRQ_M_SOFT)
> -#define MIP_STIP (1 << IRQ_S_TIMER)
> -#define MIP_HTIP (1 << IRQ_H_TIMER)
> -#define MIP_MTIP (1 << IRQ_M_TIMER)
> -#define MIP_SEIP (1 << IRQ_S_EXT)
> -#define MIP_HEIP (1 << IRQ_H_EXT)
> -#define MIP_MEIP (1 << IRQ_M_EXT)
> -
> -#define SIP_SSIP MIP_SSIP
> -#define SIP_STIP MIP_STIP
> -#define SIP_SEIP MIP_SEIP
> -
> +/* Privilege modes */
> #define PRV_U 0
> #define PRV_S 1
> #define PRV_H 2
> #define PRV_M 3
>
> -/* privileged ISA 1.9.1 VM modes (mstatus.vm) */
> -#define VM_1_09_MBARE 0
> -#define VM_1_09_MBB 1
> -#define VM_1_09_MBBID 2
> -#define VM_1_09_SV32 8
> -#define VM_1_09_SV39 9
> -#define VM_1_09_SV48 10
> -
> -/* privileged ISA 1.10.0 VM modes (satp.mode) */
> -#define VM_1_10_MBARE 0
> -#define VM_1_10_SV32 1
> -#define VM_1_10_SV39 8
> -#define VM_1_10_SV48 9
> -#define VM_1_10_SV57 10
> -#define VM_1_10_SV64 11
> -
> -/* privileged ISA interrupt causes */
> -#define IRQ_U_SOFT 0 /* since: priv-1.10 */
> -#define IRQ_S_SOFT 1
> -#define IRQ_H_SOFT 2 /* until: priv-1.9.1 */
> -#define IRQ_M_SOFT 3 /* until: priv-1.9.1 */
> -#define IRQ_U_TIMER 4 /* since: priv-1.10 */
> -#define IRQ_S_TIMER 5
> -#define IRQ_H_TIMER 6 /* until: priv-1.9.1 */
> -#define IRQ_M_TIMER 7 /* until: priv-1.9.1 */
> -#define IRQ_U_EXT 8 /* since: priv-1.10 */
> -#define IRQ_S_EXT 9
> -#define IRQ_H_EXT 10 /* until: priv-1.9.1 */
> -#define IRQ_M_EXT 11 /* until: priv-1.9.1 */
> -#define IRQ_X_COP 12 /* non-standard */
> -
> -/* Default addresses */
> -#define DEFAULT_RSTVEC 0x00001000
> -
> -/* RV32 satp field masks */
> -#define SATP32_MODE 0x80000000
> -#define SATP32_ASID 0x7fc00000
> -#define SATP32_PPN 0x003fffff
> -
> -/* RV64 satp field masks */
> -#define SATP64_MODE 0xF000000000000000ULL
> -#define SATP64_ASID 0x0FFFF00000000000ULL
> -#define SATP64_PPN 0x00000FFFFFFFFFFFULL
> +/* RV32 satp CSR field masks */
> +#define SATP32_MODE 0x80000000
> +#define SATP32_ASID 0x7fc00000
> +#define SATP32_PPN 0x003fffff
> +
> +/* RV64 satp CSR field masks */
> +#define SATP64_MODE 0xF000000000000000ULL
> +#define SATP64_ASID 0x0FFFF00000000000ULL
> +#define SATP64_PPN 0x00000FFFFFFFFFFFULL
>
> #if defined(TARGET_RISCV32)
> -#define SATP_MODE SATP32_MODE
> -#define SATP_ASID SATP32_ASID
> -#define SATP_PPN SATP32_PPN
> +#define SATP_MODE SATP32_MODE
> +#define SATP_ASID SATP32_ASID
> +#define SATP_PPN SATP32_PPN
> #endif
> #if defined(TARGET_RISCV64)
> -#define SATP_MODE SATP64_MODE
> -#define SATP_ASID SATP64_ASID
> -#define SATP_PPN SATP64_PPN
> +#define SATP_MODE SATP64_MODE
> +#define SATP_ASID SATP64_ASID
> +#define SATP_PPN SATP64_PPN
> #endif
>
> -/* RISCV Exception Codes */
> -#define EXCP_NONE -1 /* not a real RISCV exception code */
> +/* VM modes (mstatus.vm) privileged ISA 1.9.1 */
> +#define VM_1_09_MBARE 0
> +#define VM_1_09_MBB 1
> +#define VM_1_09_MBBID 2
> +#define VM_1_09_SV32 8
> +#define VM_1_09_SV39 9
> +#define VM_1_09_SV48 10
> +
> +/* VM modes (satp.mode) privileged ISA 1.10 */
> +#define VM_1_10_MBARE 0
> +#define VM_1_10_SV32 1
> +#define VM_1_10_SV39 8
> +#define VM_1_10_SV48 9
> +#define VM_1_10_SV57 10
> +#define VM_1_10_SV64 11
> +
> +/* Page table entry (PTE) fields */
> +#define PTE_V 0x001 /* Valid */
> +#define PTE_R 0x002 /* Read */
> +#define PTE_W 0x004 /* Write */
> +#define PTE_X 0x008 /* Execute */
> +#define PTE_U 0x010 /* User */
> +#define PTE_G 0x020 /* Global */
> +#define PTE_A 0x040 /* Accessed */
> +#define PTE_D 0x080 /* Dirty */
> +#define PTE_SOFT 0x300 /* Reserved for Software */
> +
> +/* Page table PPN shift amount */
> +#define PTE_PPN_SHIFT 10
> +
> +/* Leaf page shift amount */
> +#define PGSHIFT 12
> +
> +/* Default Reset Vector adress */
> +#define DEFAULT_RSTVEC 0x1000
> +
> +/* Exception causes */
> +#define EXCP_NONE -1 /* sentinel value */
> #define RISCV_EXCP_INST_ADDR_MIS 0x0
> #define RISCV_EXCP_INST_ACCESS_FAULT 0x1
> #define RISCV_EXCP_ILLEGAL_INST 0x2
> @@ -382,9 +411,7 @@
> #define RISCV_EXCP_LOAD_ACCESS_FAULT 0x5
> #define RISCV_EXCP_STORE_AMO_ADDR_MIS 0x6
> #define RISCV_EXCP_STORE_AMO_ACCESS_FAULT 0x7
> -#define RISCV_EXCP_U_ECALL 0x8 /* for convenience, report all
> - ECALLs as this, handler
> - fixes */
> +#define RISCV_EXCP_U_ECALL 0x8
> #define RISCV_EXCP_S_ECALL 0x9
> #define RISCV_EXCP_H_ECALL 0xa
> #define RISCV_EXCP_M_ECALL 0xb
> @@ -395,15 +422,35 @@
> #define RISCV_EXCP_INT_FLAG 0x80000000
> #define RISCV_EXCP_INT_MASK 0x7fffffff
>
> -/* page table entry (PTE) fields */
> -#define PTE_V 0x001 /* Valid */
> -#define PTE_R 0x002 /* Read */
> -#define PTE_W 0x004 /* Write */
> -#define PTE_X 0x008 /* Execute */
> -#define PTE_U 0x010 /* User */
> -#define PTE_G 0x020 /* Global */
> -#define PTE_A 0x040 /* Accessed */
> -#define PTE_D 0x080 /* Dirty */
> -#define PTE_SOFT 0x300 /* Reserved for Software */
> -
> -#define PTE_PPN_SHIFT 10
> +/* Interrupt causes */
> +#define IRQ_U_SOFT 0
> +#define IRQ_S_SOFT 1
> +#define IRQ_H_SOFT 2 /* reserved */
> +#define IRQ_M_SOFT 3
> +#define IRQ_U_TIMER 4
> +#define IRQ_S_TIMER 5
> +#define IRQ_H_TIMER 6 /* reserved */
> +#define IRQ_M_TIMER 7
> +#define IRQ_U_EXT 8
> +#define IRQ_S_EXT 9
> +#define IRQ_H_EXT 10 /* reserved */
> +#define IRQ_M_EXT 11
> +
> +/* mip masks */
> +#define MIP_USIP (1 << IRQ_U_SOFT)
> +#define MIP_SSIP (1 << IRQ_S_SOFT)
> +#define MIP_HSIP (1 << IRQ_H_SOFT)
> +#define MIP_MSIP (1 << IRQ_M_SOFT)
> +#define MIP_UTIP (1 << IRQ_U_TIMER)
> +#define MIP_STIP (1 << IRQ_S_TIMER)
> +#define MIP_HTIP (1 << IRQ_H_TIMER)
> +#define MIP_MTIP (1 << IRQ_M_TIMER)
> +#define MIP_UEIP (1 << IRQ_U_EXT)
> +#define MIP_SEIP (1 << IRQ_S_EXT)
> +#define MIP_HEIP (1 << IRQ_H_EXT)
> +#define MIP_MEIP (1 << IRQ_M_EXT)
> +
> +/* sip masks */
> +#define SIP_SSIP MIP_SSIP
> +#define SIP_STIP MIP_STIP
> +#define SIP_SEIP MIP_SEIP
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 495390ab1c..3726299d4a 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -90,7 +90,7 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
> target_ulong csrno)
> {
> #ifndef CONFIG_USER_ONLY
> - uint64_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_X_COP);
> + uint64_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP;
> uint64_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
> #endif
>
> --
> 2.17.1
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v1 4/5] RISC-V: Add missing free for plic_hart_config
2018-10-08 18:25 [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches Alistair Francis
` (2 preceding siblings ...)
2018-10-08 18:25 ` [Qemu-devel] [PATCH v1 3/5] RISC-V: Update CSR and interrupt definitions Alistair Francis
@ 2018-10-08 18:25 ` Alistair Francis
2018-10-10 19:10 ` Philippe Mathieu-Daudé
2018-10-10 20:03 ` Palmer Dabbelt
2018-10-08 18:25 ` [Qemu-devel] [PATCH v1 5/5] RISC-V: Don't add NULL bootargs to device-tree Alistair Francis
2018-10-10 17:49 ` [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches Palmer Dabbelt
5 siblings, 2 replies; 25+ messages in thread
From: Alistair Francis @ 2018-10-08 18:25 UTC (permalink / raw)
To: qemu-devel@nongnu.org, mjc@sifive.com
Cc: Alistair Francis, alistair23@gmail.com
From: Michael Clark <mjc@sifive.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 005169eabc..6bd723dc3a 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -385,6 +385,8 @@ static void riscv_virt_board_init(MachineState *machine)
serial_mm_init(system_memory, memmap[VIRT_UART0].base,
0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
serial_hd(0), DEVICE_LITTLE_ENDIAN);
+
+ g_free(plic_hart_config);
}
static void riscv_virt_board_machine_init(MachineClass *mc)
--
2.17.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [Qemu-devel] [PATCH v1 4/5] RISC-V: Add missing free for plic_hart_config
2018-10-08 18:25 ` [Qemu-devel] [PATCH v1 4/5] RISC-V: Add missing free for plic_hart_config Alistair Francis
@ 2018-10-10 19:10 ` Philippe Mathieu-Daudé
2018-10-10 20:03 ` Palmer Dabbelt
1 sibling, 0 replies; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-10-10 19:10 UTC (permalink / raw)
To: Alistair Francis, qemu-devel@nongnu.org, mjc@sifive.com
Cc: alistair23@gmail.com
On 08/10/2018 20:25, Alistair Francis wrote:
> From: Michael Clark <mjc@sifive.com>
>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/riscv/virt.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 005169eabc..6bd723dc3a 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -385,6 +385,8 @@ static void riscv_virt_board_init(MachineState *machine)
> serial_mm_init(system_memory, memmap[VIRT_UART0].base,
> 0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
> serial_hd(0), DEVICE_LITTLE_ENDIAN);
> +
> + g_free(plic_hart_config);
> }
>
> static void riscv_virt_board_machine_init(MachineClass *mc)
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v1 4/5] RISC-V: Add missing free for plic_hart_config
2018-10-08 18:25 ` [Qemu-devel] [PATCH v1 4/5] RISC-V: Add missing free for plic_hart_config Alistair Francis
2018-10-10 19:10 ` Philippe Mathieu-Daudé
@ 2018-10-10 20:03 ` Palmer Dabbelt
1 sibling, 0 replies; 25+ messages in thread
From: Palmer Dabbelt @ 2018-10-10 20:03 UTC (permalink / raw)
Cc: qemu-devel, Michael Clark, alistair23, Alistair.Francis
On Mon, 08 Oct 2018 11:25:45 PDT (-0700), Alistair.Francis@wdc.com wrote:
> From: Michael Clark <mjc@sifive.com>
>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/virt.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 005169eabc..6bd723dc3a 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -385,6 +385,8 @@ static void riscv_virt_board_init(MachineState *machine)
> serial_mm_init(system_memory, memmap[VIRT_UART0].base,
> 0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
> serial_hd(0), DEVICE_LITTLE_ENDIAN);
> +
> + g_free(plic_hart_config);
> }
>
> static void riscv_virt_board_machine_init(MachineClass *mc)
> --
> 2.17.1
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v1 5/5] RISC-V: Don't add NULL bootargs to device-tree
2018-10-08 18:25 [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches Alistair Francis
` (3 preceding siblings ...)
2018-10-08 18:25 ` [Qemu-devel] [PATCH v1 4/5] RISC-V: Add missing free for plic_hart_config Alistair Francis
@ 2018-10-08 18:25 ` Alistair Francis
2018-10-10 19:06 ` Philippe Mathieu-Daudé
2018-10-10 20:03 ` Palmer Dabbelt
2018-10-10 17:49 ` [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches Palmer Dabbelt
5 siblings, 2 replies; 25+ messages in thread
From: Alistair Francis @ 2018-10-08 18:25 UTC (permalink / raw)
To: qemu-devel@nongnu.org, mjc@sifive.com
Cc: Alistair Francis, alistair23@gmail.com
From: Michael Clark <mjc@sifive.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_u.c | 4 +++-
hw/riscv/spike.c | 6 ++++--
hw/riscv/virt.c | 4 +++-
3 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 862f8ff5f7..ef07df2442 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -230,7 +230,9 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
qemu_fdt_add_subnode(fdt, "/chosen");
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
- qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+ if (cmdline) {
+ qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+ }
g_free(nodename);
}
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index be5ef85e81..8a712ed490 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -156,8 +156,10 @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
g_free(cells);
g_free(nodename);
- qemu_fdt_add_subnode(fdt, "/chosen");
- qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+ if (cmdline) {
+ qemu_fdt_add_subnode(fdt, "/chosen");
+ qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+ }
}
static void spike_v1_10_0_board_init(MachineState *machine)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 6bd723dc3a..4a137a503c 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -254,7 +254,9 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
qemu_fdt_add_subnode(fdt, "/chosen");
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
- qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+ if (cmdline) {
+ qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+ }
g_free(nodename);
return fdt;
--
2.17.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [Qemu-devel] [PATCH v1 5/5] RISC-V: Don't add NULL bootargs to device-tree
2018-10-08 18:25 ` [Qemu-devel] [PATCH v1 5/5] RISC-V: Don't add NULL bootargs to device-tree Alistair Francis
@ 2018-10-10 19:06 ` Philippe Mathieu-Daudé
2018-10-10 20:03 ` Palmer Dabbelt
1 sibling, 0 replies; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-10-10 19:06 UTC (permalink / raw)
To: Alistair Francis, qemu-devel@nongnu.org, mjc@sifive.com
Cc: alistair23@gmail.com
On 08/10/2018 20:25, Alistair Francis wrote:
> From: Michael Clark <mjc@sifive.com>
>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/riscv/sifive_u.c | 4 +++-
> hw/riscv/spike.c | 6 ++++--
> hw/riscv/virt.c | 4 +++-
> 3 files changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 862f8ff5f7..ef07df2442 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -230,7 +230,9 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
>
> qemu_fdt_add_subnode(fdt, "/chosen");
> qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
> - qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
> + if (cmdline) {
> + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
> + }
> g_free(nodename);
> }
>
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index be5ef85e81..8a712ed490 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -156,8 +156,10 @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
> g_free(cells);
> g_free(nodename);
>
> - qemu_fdt_add_subnode(fdt, "/chosen");
> - qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
> + if (cmdline) {
> + qemu_fdt_add_subnode(fdt, "/chosen");
> + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
> + }
> }
>
> static void spike_v1_10_0_board_init(MachineState *machine)
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 6bd723dc3a..4a137a503c 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -254,7 +254,9 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
>
> qemu_fdt_add_subnode(fdt, "/chosen");
> qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
> - qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
> + if (cmdline) {
> + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
> + }
> g_free(nodename);
>
> return fdt;
>
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [Qemu-devel] [PATCH v1 5/5] RISC-V: Don't add NULL bootargs to device-tree
2018-10-08 18:25 ` [Qemu-devel] [PATCH v1 5/5] RISC-V: Don't add NULL bootargs to device-tree Alistair Francis
2018-10-10 19:06 ` Philippe Mathieu-Daudé
@ 2018-10-10 20:03 ` Palmer Dabbelt
1 sibling, 0 replies; 25+ messages in thread
From: Palmer Dabbelt @ 2018-10-10 20:03 UTC (permalink / raw)
Cc: qemu-devel, Michael Clark, alistair23, Alistair.Francis
On Mon, 08 Oct 2018 11:25:56 PDT (-0700), Alistair.Francis@wdc.com wrote:
> From: Michael Clark <mjc@sifive.com>
>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/sifive_u.c | 4 +++-
> hw/riscv/spike.c | 6 ++++--
> hw/riscv/virt.c | 4 +++-
> 3 files changed, 10 insertions(+), 4 deletions(-)
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 862f8ff5f7..ef07df2442 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -230,7 +230,9 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
>
> qemu_fdt_add_subnode(fdt, "/chosen");
> qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
> - qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
> + if (cmdline) {
> + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
> + }
> g_free(nodename);
> }
>
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index be5ef85e81..8a712ed490 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -156,8 +156,10 @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
> g_free(cells);
> g_free(nodename);
>
> - qemu_fdt_add_subnode(fdt, "/chosen");
> - qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
> + if (cmdline) {
> + qemu_fdt_add_subnode(fdt, "/chosen");
> + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
> + }
> }
>
> static void spike_v1_10_0_board_init(MachineState *machine)
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 6bd723dc3a..4a137a503c 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -254,7 +254,9 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
>
> qemu_fdt_add_subnode(fdt, "/chosen");
> qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
> - qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
> + if (cmdline) {
> + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
> + }
> g_free(nodename);
>
> return fdt;
> --
> 2.17.1
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches
2018-10-08 18:25 [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches Alistair Francis
` (4 preceding siblings ...)
2018-10-08 18:25 ` [Qemu-devel] [PATCH v1 5/5] RISC-V: Don't add NULL bootargs to device-tree Alistair Francis
@ 2018-10-10 17:49 ` Palmer Dabbelt
2018-10-10 18:10 ` Peter Maydell
5 siblings, 1 reply; 25+ messages in thread
From: Palmer Dabbelt @ 2018-10-10 17:49 UTC (permalink / raw)
Cc: qemu-devel, Michael Clark, alistair23, Alistair.Francis
On Mon, 08 Oct 2018 11:25:07 PDT (-0700), Alistair.Francis@wdc.com wrote:
> These are some patches that I have cherry picked from Michael's RISC-V
> tree that are ready to be applied.
> Unless anyone has any comments against these I'll send a PR later this
> week.
>
> Michael Clark (5):
> RISC-V: Allow setting and clearing multiple irqs
> RISC-V: Move non-ops from op_helper to cpu_helper
> RISC-V: Update CSR and interrupt definitions
> RISC-V: Add missing free for plic_hart_config
> RISC-V: Don't add NULL bootargs to device-tree
>
> hw/riscv/sifive_clint.c | 8 +-
> hw/riscv/sifive_plic.c | 4 +-
> hw/riscv/sifive_u.c | 4 +-
> hw/riscv/spike.c | 6 +-
> hw/riscv/virt.c | 6 +-
> target/riscv/Makefile.objs | 2 +-
> target/riscv/cpu.c | 6 +-
> target/riscv/cpu.h | 22 +-
> target/riscv/cpu_bits.h | 683 +++++++++++++-----------
> target/riscv/{helper.c => cpu_helper.c} | 35 +-
> target/riscv/op_helper.c | 34 +-
> 11 files changed, 438 insertions(+), 372 deletions(-)
> rename target/riscv/{helper.c => cpu_helper.c} (95%)
I tried pinging Michael but he hasn't responded. As far as I'm concerned, as
long as you've tested these then they seem fine -- they look pretty safe. If
you're not set up to make QEMU PRs then I can do so, as we should really get
the ball rolling on our big patch backlog.
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches
2018-10-10 17:49 ` [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches Palmer Dabbelt
@ 2018-10-10 18:10 ` Peter Maydell
2018-10-10 18:14 ` Alistair
2018-10-10 18:22 ` Palmer Dabbelt
0 siblings, 2 replies; 25+ messages in thread
From: Peter Maydell @ 2018-10-10 18:10 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Alistair Francis, Alistair Francis, Michael Clark,
QEMU Developers
On 10 October 2018 at 18:49, Palmer Dabbelt <palmer@sifive.com> wrote:
> we should really
> get the ball rolling on our big patch backlog.
Yes, please do. Softfreeze is not all that far away and I
would strongly prefer not to get an enormous sized pull
request at the last minute. The ideal pattern is that
code changes come in at a steady rate across the whole
of the 'open' part of the development cycle.
thanks
-- PMM
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches
2018-10-10 18:10 ` Peter Maydell
@ 2018-10-10 18:14 ` Alistair
2018-10-10 18:22 ` Palmer Dabbelt
1 sibling, 0 replies; 25+ messages in thread
From: Alistair @ 2018-10-10 18:14 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt
Cc: Alistair Francis, Michael Clark, QEMU Developers
On 10/10/2018 11:10 AM, Peter Maydell wrote:
> On 10 October 2018 at 18:49, Palmer Dabbelt <palmer@sifive.com> wrote:
>> we should really
>> get the ball rolling on our big patch backlog.
>
> Yes, please do. Softfreeze is not all that far away and I
> would strongly prefer not to get an enormous sized pull
> request at the last minute. The ideal pattern is that
> code changes come in at a steady rate across the whole
> of the 'open' part of the development cycle.
Understandable. I'll send a PR in the next few days. I'm hoping I can
bundle it with my PCIe patches which are just waiting on some discussion.
Alistair
>
> thanks
> -- PMM
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches
2018-10-10 18:10 ` Peter Maydell
2018-10-10 18:14 ` Alistair
@ 2018-10-10 18:22 ` Palmer Dabbelt
2018-10-11 9:34 ` Peter Maydell
2018-10-11 20:52 ` Michael Clark
1 sibling, 2 replies; 25+ messages in thread
From: Palmer Dabbelt @ 2018-10-10 18:22 UTC (permalink / raw)
To: peter.maydell; +Cc: Alistair.Francis, alistair23, Michael Clark, qemu-devel
On Wed, 10 Oct 2018 11:10:07 PDT (-0700), peter.maydell@linaro.org wrote:
> On 10 October 2018 at 18:49, Palmer Dabbelt <palmer@sifive.com> wrote:
>> we should really
>> get the ball rolling on our big patch backlog.
>
> Yes, please do. Softfreeze is not all that far away and I
> would strongly prefer not to get an enormous sized pull
> request at the last minute. The ideal pattern is that
> code changes come in at a steady rate across the whole
> of the 'open' part of the development cycle.
Ya, sorry, we've been a bit out of it. If I understand correctly, the soft
freeze is the 30th? If so it's really time to get started, and it looks like
Michael is busy so I'll have to go figure this out.
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches
2018-10-10 18:22 ` Palmer Dabbelt
@ 2018-10-11 9:34 ` Peter Maydell
2018-10-12 0:11 ` Palmer Dabbelt
2018-10-11 20:52 ` Michael Clark
1 sibling, 1 reply; 25+ messages in thread
From: Peter Maydell @ 2018-10-11 9:34 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Alistair Francis, Alistair Francis, Michael Clark,
QEMU Developers
On 10 October 2018 at 19:22, Palmer Dabbelt <palmer@sifive.com> wrote:
> On Wed, 10 Oct 2018 11:10:07 PDT (-0700), peter.maydell@linaro.org wrote:
>>
>> On 10 October 2018 at 18:49, Palmer Dabbelt <palmer@sifive.com> wrote:
>>>
>>> we should really
>>> get the ball rolling on our big patch backlog.
>>
>>
>> Yes, please do. Softfreeze is not all that far away and I
>> would strongly prefer not to get an enormous sized pull
>> request at the last minute. The ideal pattern is that
>> code changes come in at a steady rate across the whole
>> of the 'open' part of the development cycle.
>
>
> Ya, sorry, we've been a bit out of it. If I understand correctly, the soft
> freeze is the 30th? If so it's really time to get started, and it looks
> like Michael is busy so I'll have to go figure this out.
Alistair's done the last couple of riscv pullrequests, so it might
be simpler if he keeps doing that, but I'll let you sort that out
between yourselves.
thanks
-- PMM
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches
2018-10-11 9:34 ` Peter Maydell
@ 2018-10-12 0:11 ` Palmer Dabbelt
0 siblings, 0 replies; 25+ messages in thread
From: Palmer Dabbelt @ 2018-10-12 0:11 UTC (permalink / raw)
To: peter.maydell; +Cc: Alistair.Francis, alistair23, Michael Clark, qemu-devel
On Thu, 11 Oct 2018 02:34:16 PDT (-0700), peter.maydell@linaro.org wrote:
> On 10 October 2018 at 19:22, Palmer Dabbelt <palmer@sifive.com> wrote:
>> On Wed, 10 Oct 2018 11:10:07 PDT (-0700), peter.maydell@linaro.org wrote:
>>>
>>> On 10 October 2018 at 18:49, Palmer Dabbelt <palmer@sifive.com> wrote:
>>>>
>>>> we should really
>>>> get the ball rolling on our big patch backlog.
>>>
>>>
>>> Yes, please do. Softfreeze is not all that far away and I
>>> would strongly prefer not to get an enormous sized pull
>>> request at the last minute. The ideal pattern is that
>>> code changes come in at a steady rate across the whole
>>> of the 'open' part of the development cycle.
>>
>>
>> Ya, sorry, we've been a bit out of it. If I understand correctly, the soft
>> freeze is the 30th? If so it's really time to get started, and it looks
>> like Michael is busy so I'll have to go figure this out.
>
> Alistair's done the last couple of riscv pullrequests, so it might
> be simpler if he keeps doing that, but I'll let you sort that out
> between yourselves.
Ah, great. I'm always happy to have other people do things, I just feel kind
of bad: I'm a maintainer and I'm putting the burden on someone else to submit a
PR.
If Alistair is happy submitting PRs than I'm happy to have him do it :).
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches
2018-10-10 18:22 ` Palmer Dabbelt
2018-10-11 9:34 ` Peter Maydell
@ 2018-10-11 20:52 ` Michael Clark
2018-10-12 9:34 ` Peter Maydell
1 sibling, 1 reply; 25+ messages in thread
From: Michael Clark @ 2018-10-11 20:52 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Peter Maydell, Alistair Francis, Alistair Francis,
QEMU Developers, Sagar Karandikar, Bastian Koppelmann,
Richard Henderson, Karsten Merker, Stefan O'Rear,
Richard W.M. Jones
Hi All,
On Thu, Oct 11, 2018 at 7:22 AM Palmer Dabbelt <palmer@sifive.com> wrote:
> On Wed, 10 Oct 2018 11:10:07 PDT (-0700), peter.maydell@linaro.org wrote:
> > On 10 October 2018 at 18:49, Palmer Dabbelt <palmer@sifive.com> wrote:
> >> we should really
> >> get the ball rolling on our big patch backlog.
> >
> > Yes, please do. Softfreeze is not all that far away and I
> > would strongly prefer not to get an enormous sized pull
> > request at the last minute. The ideal pattern is that
> > code changes come in at a steady rate across the whole
> > of the 'open' part of the development cycle.
>
> Ya, sorry, we've been a bit out of it. If I understand correctly, the
> soft
> freeze is the 30th? If so it's really time to get started, and it looks
> like
> Michael is busy so I'll have to go figure this out.
>
Yes. I should think twice about the Signed-off-by: on my commits. I need to
run a regression on this out-of-order subset. I currently only run tests on
the top of the riscv-qemu tree in-order, and when I rebase against master.
If the commits need any significant effort to rebase because they are taken
in some random order then the testing will be invalidated. i.e. I haven't
checked the dependencies for these commits.
I am happy to review whoever posts the contents of the tree. I can test
apply the PRs against the riscv-qemu tree and if they give us lumps, we'll
reject, including my own changes (if rebased).
Alastair, I suggest you confer with Debian and Fedora folk. Don't break the
Linux distros... I'm petrified that we might break Debian.
Palmer, I disagree with idea, I would like to maintain the soft-fork until
we have the CI running our regression test suite (currently manual)
Peter, I have to pull in your remote wholesale. I don't cherry-pick from
your tree. I think this is truly dumb. This might serve the needs of some
folk running Linux but we have emulation fidelity fixes for the RISC-V
community as a whole. Alastair is the only person not submitting his
patches via the (sub)maintainer tree. BTW Who is the RISC-V port
maintainer? Puzzled.
Here is the pull queue. But I'm not ready to make a PR until we have the CI
running the regression. I certainly don't want rebases of random commits to
the riscv-qemu tree coming in when we pull.
- https://github.com/riscv/riscv-qemu/tree/qemu-for-upstream
That said, they have sign-off. There are plenty of other "RISC-V"
maintainers. Do what you think is wise.
Most important thing here is the Debian builders and other RISC-V virtual
machines in production. Having the Debian folk or some other helpful tester
running the entire tree. Pulling it in one go means we don't have a
bisection problem interspersed with a whole lot of other random patches.
You may not have all of the interrupt related changes that require
extensive parallel burn-in tests (GCC bootstrap). i.e. we do significantly
more than "make check" when we pull changes into our tree.
Thanks and Regards,
Michael.
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches
2018-10-11 20:52 ` Michael Clark
@ 2018-10-12 9:34 ` Peter Maydell
2018-10-15 20:28 ` Palmer Dabbelt
0 siblings, 1 reply; 25+ messages in thread
From: Peter Maydell @ 2018-10-12 9:34 UTC (permalink / raw)
To: Michael Clark
Cc: Palmer Dabbelt, Alistair Francis, Alistair Francis,
QEMU Developers, Sagar Karandikar, Bastian Koppelmann,
Richard Henderson, Karsten Merker, Stefan O'Rear,
Richard W.M. Jones
On 11 October 2018 at 21:52, Michael Clark <mjc@sifive.com> wrote:
> Peter, I have to pull in your remote wholesale. I don't cherry-pick from
> your tree. I think this is truly dumb. This might serve the needs of some
> folk running Linux but we have emulation fidelity fixes for the RISC-V
> community as a whole. Alastair is the only person not submitting his patches
> via the (sub)maintainer tree. BTW Who is the RISC-V port maintainer?
> Puzzled.
I don't particularly mind who among you RISC-V folk does the QEMU
submaintainer work. But I would like to see somebody doing it,
and sitting on all your patches indefinitely in an out-of-tree
fork is not doing that job. There is no obligation to work
with upstream on a RISC-V QEMU, of course. But your last
pull request was back in May, so it's not surprising if
other people offer to step into that gap.
If you have emulation fidelity fixes, then the best approach
is to work on getting them upstream.
If you have downstream consumers for whom you want to maintain
a validated definitely-works tree, that's great. How you
manage that downstream tree (when you rebase it, what you
put in it, whether you make it have formal "releases", etc)
is up to you. I would suggest that trying to make it be the
same thing as your development tree for pushing work upstream
is not likely to serve either purpose well, though.
The expected patch flow for QEMU is:
* original patch author posts patch to qemu-devel
(this applies also if the author happens to be the
submaintainer)
* patch gets reviewed on this mailing list, by you or
anybody else
* patches relevant to risc-v get collected up by the
submaintainer
* submaintainer submits those patches via pull request
(with a frequency usually about every two weeks, more
often if volume of patches merits it)
> Here is the pull queue. But I'm not ready to make a PR until we have the CI
> running the regression.
This phrasing suggests you might be thinking about making a
large batch pull request all at once close to the
freeze deadline. That would be a bad idea -- it did not
work well last release either. Patches are best dribbled
into upstream at a steady pace as they are written.
(Note also that pull requests should not contain patches
which have not already been posted to qemu-devel and
reviewed here.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches
2018-10-12 9:34 ` Peter Maydell
@ 2018-10-15 20:28 ` Palmer Dabbelt
2018-10-16 8:05 ` Peter Maydell
0 siblings, 1 reply; 25+ messages in thread
From: Palmer Dabbelt @ 2018-10-15 20:28 UTC (permalink / raw)
To: peter.maydell
Cc: Michael Clark, Alistair.Francis, alistair23, qemu-devel, sagark,
kbastian, richard.henderson, merker, sorear2, rjones
On Fri, 12 Oct 2018 02:34:12 PDT (-0700), peter.maydell@linaro.org wrote:
> On 11 October 2018 at 21:52, Michael Clark <mjc@sifive.com> wrote:
>> Peter, I have to pull in your remote wholesale. I don't cherry-pick from
>> your tree. I think this is truly dumb. This might serve the needs of some
>> folk running Linux but we have emulation fidelity fixes for the RISC-V
>> community as a whole. Alastair is the only person not submitting his patches
>> via the (sub)maintainer tree. BTW Who is the RISC-V port maintainer?
>> Puzzled.
>
> I don't particularly mind who among you RISC-V folk does the QEMU
> submaintainer work. But I would like to see somebody doing it,
> and sitting on all your patches indefinitely in an out-of-tree
> fork is not doing that job. There is no obligation to work
> with upstream on a RISC-V QEMU, of course. But your last
> pull request was back in May, so it's not surprising if
> other people offer to step into that gap.
>
> If you have emulation fidelity fixes, then the best approach
> is to work on getting them upstream.
I agree. I think the best bet here is to just start picking through the
patches and submitting those that we have high confidence in -- there's a
handful of known bugs that have been fixed in Michael's tree.
> If you have downstream consumers for whom you want to maintain
> a validated definitely-works tree, that's great. How you
> manage that downstream tree (when you rebase it, what you
> put in it, whether you make it have formal "releases", etc)
> is up to you. I would suggest that trying to make it be the
> same thing as your development tree for pushing work upstream
> is not likely to serve either purpose well, though.
>
> The expected patch flow for QEMU is:
> * original patch author posts patch to qemu-devel
> (this applies also if the author happens to be the
> submaintainer)
> * patch gets reviewed on this mailing list, by you or
> anybody else
> * patches relevant to risc-v get collected up by the
> submaintainer
> * submaintainer submits those patches via pull request
> (with a frequency usually about every two weeks, more
> often if volume of patches merits it)
This makes sense. It's almost exactly the Linux flow, which I'm used to and I
have down to a fairly mechanical process. I think the real issue here is that
we don't have anyone who has officially committed to doing this, so I'm just
going to pull the trigger and say I'm doing so.
My Linux PR flow is to tag a PR on Mondays, send it out to the list for
comments, and then if it passes muster to submit an official PR on Wednesdays.
It's been working smoothly (we've yet to have to kill a PR), so I think I'll do
the same thing for QEMU except I'll do Tuesday/Thursday.
I talked to Michael on the phone late last week and he seemed OK with this.
>> Here is the pull queue. But I'm not ready to make a PR until we have the CI
>> running the regression.
>
> This phrasing suggests you might be thinking about making a
> large batch pull request all at once close to the
> freeze deadline. That would be a bad idea -- it did not
> work well last release either. Patches are best dribbled
> into upstream at a steady pace as they are written.
> (Note also that pull requests should not contain patches
> which have not already been posted to qemu-devel and
> reviewed here.)
>
> thanks
> -- PMM
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches
2018-10-15 20:28 ` Palmer Dabbelt
@ 2018-10-16 8:05 ` Peter Maydell
2018-10-16 18:35 ` Palmer Dabbelt
0 siblings, 1 reply; 25+ messages in thread
From: Peter Maydell @ 2018-10-16 8:05 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Michael Clark, Alistair Francis, Alistair Francis,
QEMU Developers, Sagar Karandikar, Bastian Koppelmann,
Richard Henderson, Karsten Merker, Stef O'Rear,
Richard W.M. Jones
On 15 October 2018 at 21:28, Palmer Dabbelt <palmer@sifive.com> wrote:
> On Fri, 12 Oct 2018 02:34:12 PDT (-0700), peter.maydell@linaro.org wrote:
>> The expected patch flow for QEMU is:
>> * original patch author posts patch to qemu-devel
>> (this applies also if the author happens to be the
>> submaintainer)
>> * patch gets reviewed on this mailing list, by you or
>> anybody else
>> * patches relevant to risc-v get collected up by the
>> submaintainer
>> * submaintainer submits those patches via pull request
>> (with a frequency usually about every two weeks, more
>> often if volume of patches merits it)
>
>
> This makes sense. It's almost exactly the Linux flow, which I'm used to and
> I have down to a fairly mechanical process. I think the real issue here is
> that we don't have anyone who has officially committed to doing this, so I'm
> just going to pull the trigger and say I'm doing so.
Thanks for picking this up.
> My Linux PR flow is to tag a PR on Mondays, send it out to the list for
> comments, and then if it passes muster to submit an official PR on
> Wednesdays. It's been working smoothly (we've yet to have to kill a PR), so
> I think I'll do the same thing for QEMU except I'll do Tuesday/Thursday.
For QEMU we do patches first, pull requests for reviewed stuff.
If you send a pull request out to the list the assumption is
that it's a request to apply it to master immediately.
thanks
-- PMM
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches
2018-10-16 8:05 ` Peter Maydell
@ 2018-10-16 18:35 ` Palmer Dabbelt
0 siblings, 0 replies; 25+ messages in thread
From: Palmer Dabbelt @ 2018-10-16 18:35 UTC (permalink / raw)
To: peter.maydell
Cc: Michael Clark, Alistair.Francis, alistair23, qemu-devel, sagark,
kbastian, richard.henderson, merker, sorear2, rjones
On Tue, 16 Oct 2018 01:05:11 PDT (-0700), peter.maydell@linaro.org wrote:
> On 15 October 2018 at 21:28, Palmer Dabbelt <palmer@sifive.com> wrote:
>> On Fri, 12 Oct 2018 02:34:12 PDT (-0700), peter.maydell@linaro.org wrote:
>>> The expected patch flow for QEMU is:
>>> * original patch author posts patch to qemu-devel
>>> (this applies also if the author happens to be the
>>> submaintainer)
>>> * patch gets reviewed on this mailing list, by you or
>>> anybody else
>>> * patches relevant to risc-v get collected up by the
>>> submaintainer
>>> * submaintainer submits those patches via pull request
>>> (with a frequency usually about every two weeks, more
>>> often if volume of patches merits it)
>>
>>
>> This makes sense. It's almost exactly the Linux flow, which I'm used to and
>> I have down to a fairly mechanical process. I think the real issue here is
>> that we don't have anyone who has officially committed to doing this, so I'm
>> just going to pull the trigger and say I'm doing so.
>
> Thanks for picking this up.
>
>> My Linux PR flow is to tag a PR on Mondays, send it out to the list for
>> comments, and then if it passes muster to submit an official PR on
>> Wednesdays. It's been working smoothly (we've yet to have to kill a PR), so
>> I think I'll do the same thing for QEMU except I'll do Tuesday/Thursday.
>
> For QEMU we do patches first, pull requests for reviewed stuff.
> If you send a pull request out to the list the assumption is
> that it's a request to apply it to master immediately.
Yep, that's the same as Linux. I just send the PR to the RISC-V mailing lists
marked as an RFC so it doesn't get confused. If you don't want me to do this
in QEMU land then it's fine.
^ permalink raw reply [flat|nested] 25+ messages in thread