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Wed, 14 May 2025 14:37:39 +0000 (GMT) Message-ID: <38a9bbb0-92ed-4877-912f-725bb28f6dd0@linux.ibm.com> Date: Wed, 14 May 2025 09:37:39 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 20/50] pnv/xive2: Permit valid writes to VC/PC Flush Control registers To: Nicholas Piggin , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, =?UTF-8?B?RnLDqWTDqXJpYyBCYXJyYXQ=?= , Glenn Miles , Michael Kowal , Caleb Schlossin References: <20250512031100.439842-1-npiggin@gmail.com> <20250512031100.439842-21-npiggin@gmail.com> Content-Language: en-US From: Caleb Schlossin In-Reply-To: <20250512031100.439842-21-npiggin@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 6Kj-V04g6_MlQWKnl3sKbyK5u50A2wZj X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE0MDEzMCBTYWx0ZWRfX+vt9qiJqbr4g AQWGPfcnil65E+FpvOIBda8Ach+Zs4I2zI95LXs4W9keUlkDl4OoPx52UHjVSlAi/EwC7VirAMj V4hrFcSaVb3JzlCVu3bpOcjX5V591EgAw7iuWAJhGSAC1+osWE2dnKZG1/pNL2UXyrNKaME0goi SyCK+9MMCSSd8Z1WI581nZPwryeSFdzCTNqu4t4VAMBgHZiEgpysOYEd0mN/wrqZu5Nol54wg5E TSZqYv2DzIgy29qOqIcH6dscP4KmgcGmToApcWIlVn0sMZTXZiQ5dfcZQC0bxuWWirO6iIW8geH 8DpHLtJp9n7ZpyTcU7tqYg2WWGEwzrRmYQLWQqdBBf9KJWHugy1IFZe74ZqocDHpiabeDnT9/+P /N+KV0H1ePV+pt372OyfsZwA4xr+31SjatkdIrCpi2Nshs+0pLY5taWFNtreX3j++tVpPiSx X-Proofpoint-ORIG-GUID: ff96PEEswlnmcFCKmSiDqTi4vqbIxJ3a X-Authority-Analysis: v=2.4 cv=GbEXnRXL c=1 sm=1 tr=0 ts=6824aab6 cx=c_pps a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=VnNF1IyMAAAA:8 a=K43VmlK4zf_02HQK-ZgA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-14_04,2025-05-14_03,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 suspectscore=0 mlxlogscore=770 phishscore=0 bulkscore=0 malwarescore=0 mlxscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505140130 Received-SPF: pass client-ip=148.163.158.5; envelope-from=calebs@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Wed, 14 May 2025 11:10:39 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reviewed-by: Caleb Schlossin On 5/11/25 10:10 PM, Nicholas Piggin wrote: > From: Michael Kowal > > Writes to the Flush Control registers were logged as invalid > when they are allowed. Clearing the unsupported want_cache_disable > feature is supported, so don't log an error in that case. > > Signed-off-by: Michael Kowal > --- > hw/intc/pnv_xive2.c | 36 ++++++++++++++++++++++++++++++++---- > 1 file changed, 32 insertions(+), 4 deletions(-) > > diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c > index 3c26cd6b77..c9374f0eee 100644 > --- a/hw/intc/pnv_xive2.c > +++ b/hw/intc/pnv_xive2.c > @@ -1411,7 +1411,14 @@ static void pnv_xive2_ic_vc_write(void *opaque, hwaddr offset, > /* > * ESB cache updates (not modeled) > */ > - /* case VC_ESBC_FLUSH_CTRL: */ > + case VC_ESBC_FLUSH_CTRL: > + if (val & VC_ESBC_FLUSH_CTRL_WANT_CACHE_DISABLE) { > + xive2_error(xive, "VC: unsupported write @0x%"HWADDR_PRIx > + " value 0x%"PRIx64" bit[2] poll_want_cache_disable", > + offset, val); > + return; > + } > + break; > case VC_ESBC_FLUSH_POLL: > xive->vc_regs[VC_ESBC_FLUSH_CTRL >> 3] |= VC_ESBC_FLUSH_CTRL_POLL_VALID; > /* ESB update */ > @@ -1427,7 +1434,14 @@ static void pnv_xive2_ic_vc_write(void *opaque, hwaddr offset, > /* > * EAS cache updates (not modeled) > */ > - /* case VC_EASC_FLUSH_CTRL: */ > + case VC_EASC_FLUSH_CTRL: > + if (val & VC_EASC_FLUSH_CTRL_WANT_CACHE_DISABLE) { > + xive2_error(xive, "VC: unsupported write @0x%"HWADDR_PRIx > + " value 0x%"PRIx64" bit[2] poll_want_cache_disable", > + offset, val); > + return; > + } > + break; > case VC_EASC_FLUSH_POLL: > xive->vc_regs[VC_EASC_FLUSH_CTRL >> 3] |= VC_EASC_FLUSH_CTRL_POLL_VALID; > /* EAS update */ > @@ -1466,7 +1480,14 @@ static void pnv_xive2_ic_vc_write(void *opaque, hwaddr offset, > break; > > > - /* case VC_ENDC_FLUSH_CTRL: */ > + case VC_ENDC_FLUSH_CTRL: > + if (val & VC_ENDC_FLUSH_CTRL_WANT_CACHE_DISABLE) { > + xive2_error(xive, "VC: unsupported write @0x%"HWADDR_PRIx > + " value 0x%"PRIx64" bit[2] poll_want_cache_disable", > + offset, val); > + return; > + } > + break; > case VC_ENDC_FLUSH_POLL: > xive->vc_regs[VC_ENDC_FLUSH_CTRL >> 3] |= VC_ENDC_FLUSH_CTRL_POLL_VALID; > break; > @@ -1687,7 +1708,14 @@ static void pnv_xive2_ic_pc_write(void *opaque, hwaddr offset, > pnv_xive2_nxc_update(xive, watch_engine); > break; > > - /* case PC_NXC_FLUSH_CTRL: */ > + case PC_NXC_FLUSH_CTRL: > + if (val & PC_NXC_FLUSH_CTRL_WANT_CACHE_DISABLE) { > + xive2_error(xive, "VC: unsupported write @0x%"HWADDR_PRIx > + " value 0x%"PRIx64" bit[2] poll_want_cache_disable", > + offset, val); > + return; > + } > + break; > case PC_NXC_FLUSH_POLL: > xive->pc_regs[PC_NXC_FLUSH_CTRL >> 3] |= PC_NXC_FLUSH_CTRL_POLL_VALID; > break;