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[204.210.126.223]) by smtp.gmail.com with ESMTPSA id w5sm17302142pfq.130.2021.07.18.11.50.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 18 Jul 2021 11:50:43 -0700 (PDT) Subject: Re: [PATCH v3 10/13] target/riscv: Reduce riscv_tr_breakpoint_check pc advance to 2 To: Peter Maydell References: <20210717221851.2124573-1-richard.henderson@linaro.org> <20210717221851.2124573-11-richard.henderson@linaro.org> <4d959bff-8c6b-e01b-a23b-6e17c062f85a@linaro.org> From: Richard Henderson Message-ID: <38d31fa4-e2ae-8af2-54bd-74d12a7b9470@linaro.org> Date: Sun, 18 Jul 2021 08:50:40 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.07, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , =?UTF-8?Q?Alex_Benn=c3=a9e?= , QEMU Developers , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 7/18/21 8:16 AM, Peter Maydell wrote: > On Sun, 18 Jul 2021 at 19:02, Richard Henderson > wrote: >> >> On 7/17/21 1:35 PM, Peter Maydell wrote: >>> (What goes wrong if we just say "always use a TB size of 1 regardless >>> of target arch" rather than having the arch return the worst case >>> minimum insn length?) >> >> Hmm, possibly nothing. Perhaps I should try that and see what happens... > > Some of the comments in these patches suggest it might trigger > the warning in the disassembler about length mismatches; possibly > also you might get duff (truncated) disassembly output? I suspect > that's probably the extent of the problem. We should be able to work around this by looking at tb->icount. After patch 13, when breakpoints are always at the beginning of the TB, we'll always have tb->icount == 0. Thinking about this further, with the breakpoint at the head of the TB, there's really no point in emitting code for breakpoints at all. Once we've recognized that there is a breakpoint at the current PC, we should just raise the exception. IIRC only i386 and arm have arch-specific conditional breakpoints. And, given that all cpu state is in sync when looking for bp's, we could probably make do with a callback instead of any code generation. Let me see what I can do... r~