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From: Frederic Barrat <fbarrat@linux.ibm.com>
To: "Cédric Le Goater" <clg@kaod.org>,
	danielhb413@gmail.com, qemu-ppc@nongnu.org,
	qemu-devel@nongnu.org
Subject: Re: [PATCH 4/4] pnv/xive2: Handle TIMA access through all ports
Date: Tue, 30 May 2023 19:30:46 +0200	[thread overview]
Message-ID: <38fdc4d6-ab1d-c305-c42f-0efab30c23a5@linux.ibm.com> (raw)
In-Reply-To: <b731ee69-0e1f-6eef-4c44-e6711ea39c12@kaod.org>



On 30/05/2023 18:49, Cédric Le Goater wrote:
> On 5/30/23 18:40, Cédric Le Goater wrote:
>> On 5/30/23 18:11, Frederic Barrat wrote:
>>> The Thread Interrupt Management Area (TIMA) can be accessed through 4
>>> ports/snoop buses, targeted by the address. The base address of a TIMA
>>> is using port 0 and the other ports are 0x80 apart. Using one port or
>>> another can be useful to balance the load on the snoop buses.
>>
>> and can we have some nice examples of how these ports are used ? only for
>> snooping or also for balancing operations ? which ones ?
>>
>>> The TIMA registers are in the 0x0 -> 0x3F range and there are 2
>>> indication bits for special operations (bits 10 and 11; everything
>>> fits on a 4k page). So the port address bits fall in between and are
>>> "don't care" for the hardware when processing the TIMA operation. So
>>> this patch filters out those port address bits so that a TIMA
>>> operation can be triggered using any port.
>>>
>>> It is also true for indirect access (through the IC BAR) and it's
>>> actually nothing new, it was already the case on P9. Which helps here,
>>> as the TIMA handling code is common between P9 (xive) and P10 (xive2).
>>>
>>> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
>>
>> Reviewed-by: Cédric Le Goater <clg@kaod.org>
> 
> one extra comment, since we already have one mask for the tima offsets :
> 
>      /*
>       * First, check for special operations in the 2K region
>       */
>      if (offset & 0x800) {
> 
> I think it would be cleaner to add some defines in the reg definition file.


Yeah, you're right, I should respin it with some proper defines. And 
I'll add one for the special op bit(s).

   Fred


> 
> Can come later.
> 
> Thanks,
> 
> C.
> 


  reply	other threads:[~2023-05-30 17:31 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-30 16:11 [PATCH 0/4] Various xive fixes Frederic Barrat
2023-05-30 16:11 ` [PATCH 1/4] pnv/xive2: Add definition for TCTXT Config register Frederic Barrat
2023-05-30 16:31   ` Cédric Le Goater
2023-05-30 18:01     ` Frederic Barrat
2023-05-30 16:11 ` [PATCH 2/4] pnv/xive2: Add definition for the ESB cache configuration register Frederic Barrat
2023-05-30 16:32   ` Cédric Le Goater
2023-05-30 16:11 ` [PATCH 3/4] pnv/xive2: Allow writes to the Physical Thread Enable registers Frederic Barrat
2023-05-30 16:37   ` Cédric Le Goater
2023-05-30 16:11 ` [PATCH 4/4] pnv/xive2: Handle TIMA access through all ports Frederic Barrat
2023-05-30 16:40   ` Cédric Le Goater
2023-05-30 16:49     ` Cédric Le Goater
2023-05-30 17:30       ` Frederic Barrat [this message]
2023-05-30 17:29     ` Frederic Barrat

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